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PHP69NLT Datasheet

  • PHP69NLT

  • TrenchMOS transistor Logic level FET

  • 10頁

  • ETC

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Philips Semiconductors
Product specification
TrenchMOS鈩?transistor
Logic level FET
FEATURES
鈥?/div>
鈥橳rench鈥?/div>
technology
鈥?Very low on-state resistance
鈥?Fast switching
鈥?Stable off-state characteristics
鈥?High thermal cycling performance
鈥?Low thermal resistance
PHP69N03LT, PHB69N03LT, PHD69N03LT
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 25 V
I
D
= 69 A
g
R
DS(ON)
鈮?/div>
14 m鈩?(V
GS
= 5 V)
R
DS(ON)
鈮?/div>
12 m鈩?(V
GS
= 10 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using 鈥檛rench鈥?technology.
The combination of very low on-state resistance and low switching losses make this device the optimum choice in high
speed computer motherboard d.c. to d.c. converters.
The PHP69N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB69N03LT is supplied in the SOT404 surface mounting package.
The PHD69N03LT is supplied in the SOT428 surface mounting package.
PINNING
PIN
1
2
3
tab
DESCRIPTION
SOT78 (TO220AB)
tab
SOT404
tab
SOT428
tab
gate
drain
1
source
2
2
drain
1 23
1
3
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Pulsed gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 藲C to 175藲C
T
j
= 25 藲C to 175藲C; R
GS
= 20 k鈩?/div>
T
j
鈮?/div>
150藲C
T
mb
= 25 藲C; V
GS
= 5 V
T
mb
= 100 藲C; V
GS
= 5 V
T
mb
= 25 藲C
T
mb
= 25 藲C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
25
25
鹵
15
鹵
20
69
48
240
125
175
UNIT
V
V
V
V
A
A
A
W
藲C
1
It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.
June 1998
1
Rev 1.400

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