Philips Semiconductors
Product specification
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PowerMOS transistor
PHP2N60
----------------------------------------------------------------------------------------------------------------------------------------------------------
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope featuring high
avalanche energy capability, stable
off-state
characteristics,
fast
switching and high thermal cycling
performance with low thermal
resistance. Intended for use in
Switched Mode Power Supplies
(SMPS), motor control circuits and
general
purpose
switching
applications.
QUICK REFERENCE DATA
SYMBOL
----------------
V
DS
I
D
P
tot
R
DS(ON)
PARAMETER
MAX.
UNIT
------------------------------------------------------- ----------- -----------
Drain-source voltage
600
V
Drain current (DC)
2.8
A
Total power dissipation
83
W
Drain-source on-state resistance
4.4
鈩?/div>
PINNING - TO220AB
PIN
1
2
3
tab
gate
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
d
g
1 23
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
I
D
I
DM
P
D
鈭哖
D
/鈭員
mb
V
GS
E
AS
I
AS
T
j
, T
stg
Continuous drain current
Pulsed drain current
Total dissipation
Linear derating factor
Gate-source voltage
Single pulse avalanche
energy
Peak avalanche current
Operating junction and
storage temperature range
CONDITIONS
T
mb
= 25 藲C; V
GS
= 10 V
T
mb
= 100 藲C; V
GS
= 10 V
T
mb
= 25 藲C
T
mb
= 25 藲C
T
mb
> 25 藲C
V
DD
鈮?/div>
50 V; starting T
j
= 25藲C; R
GS
= 50
鈩?
V
GS
= 10 V
V
DD
鈮?/div>
50 V; starting T
j
= 25藲C; R
GS
= 50
鈩?
V
GS
= 10 V
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
2.8
1.8
11
83
0.67
鹵
30
84
2.2
150
UNIT
A
A
A
W
W/K
V
mJ
A
藲C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
MIN.
-
-
TYP.
-
60
MAX.
1.5
-
UNIT
K/W
K/W
April 1997
1
Rev 1.001
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