鈮?/div>
50 m鈩?(V
GS
= 10 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode,
logic level, field-effect power
transistor in a plastic envelope
using 鈥檛rench鈥?technology. The
device has very low on-state
resistance. It is intended for use in
dc to dc converters and general
purpose switching applications.
The PHD24N03LT is supplied in the
SOT428 (DPAK) surface mounting
package.
PINNING
PIN
1
2
3
tab
gate
drain
1
source
DESCRIPTION
SOT428 (DPAK)
tab
2
drain
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 藲C to 175藲C
T
j
= 25 藲C to 175藲C; R
GS
= 20 k鈩?/div>
T
mb
= 25 藲C
T
mb
= 100 藲C
T
mb
= 25 藲C
T
mb
= 25 藲C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
鹵
13
24
20
96
60
175
UNIT
V
V
V
A
A
A
W
藲C
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
R
th j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
TYP.
-
pcb mounted, minimum footprint
50
MAX.
2.5
-
UNIT
K/W
K/W
1
it is not possible to make connection to pin 2 of the SOT428 package.
December 1999
1
Rev 1.100
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