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PHD21N06LT Datasheet

  • PHD21N06LT

  • TrenchMOS transistor Logic level FET

  • 10頁

  • PHILIPS

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Philips Semiconductors
Product specification
TrenchMOS鈩?transistor
Logic level FET
FEATURES
鈥?/div>
鈥橳rench鈥?/div>
technology
鈥?Very low on-state resistance
鈥?Fast switching
鈥?Stable off-state characteristics
鈥?High thermal cycling performance
鈥?Low thermal resistance
PHP21N06LT, PHB21N06LT, PHD21N06LT
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 55 V
I
D
= 21 A
g
s
R
DS(ON)
鈮?/div>
75 m鈩?(V
GS
= 5 V)
R
DS(ON)
鈮?/div>
70 m鈩?(V
GS
= 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using 鈥檛rench鈥?technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB21N06LT is supplied in the SOT404 surface mounting package.
The PHD21N06LT is supplied in the SOT428 surface mounting package.
PINNING
PIN
1
2
3
tab
DESCRIPTION
SOT78 (TO220AB)
tab
SOT404
tab
SOT428
tab
gate
drain
1
source
2
2
drain
1 23
1
3
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 藲C to 175藲C
T
j
= 25 藲C to 175藲C; R
GS
= 20 k鈩?/div>
T
mb
= 25 藲C
T
mb
= 100 藲C
T
mb
= 25 藲C
T
mb
= 25 藲C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
鹵
13
21
14.7
84
69
175
UNIT
V
V
V
A
A
A
W
藲C
1
It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.
September 1998
1
Rev 1.400

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