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PHD11N06LT Datasheet

  • PHD11N06LT

  • TrenchMOS transistor Logic level FET

  • 79.81KB

  • 9頁(yè)

  • PHILIPS

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Philips Semiconductors
Product specification
TrenchMOS鈩?transistor
Logic level FET
FEATURES
鈥?/div>
鈥橳rench鈥?/div>
technology
鈥?Very low on-state resistance
鈥?Fast switching
鈥?Stable off-state characteristics
鈥?High thermal cycling performance
鈥?Low thermal resistance
PHB11N06LT, PHD11N06LT
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 55 V
I
D
= 11 A
g
s
R
DS(ON)
鈮?/div>
150 m鈩?(V
GS
= 5 V)
R
DS(ON)
鈮?/div>
130 m鈩?(V
GS
= 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using 鈥檛rench鈥?technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHB11N06LT is supplied in the SOT404 surface mounting package.
The PHD11N06LT is supplied in the SOT428 surface mounting package.
PINNING
PIN
1
2
3
tab
gate
drain
1
source
DESCRIPTION
SOT428
tab
SOT404
tab
2
2
3
drain
1
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 藲C to 175藲C
T
j
= 25 藲C to 175藲C; R
GS
= 20 k鈩?/div>
T
mb
= 25 藲C
T
mb
= 100 藲C
T
mb
= 25 藲C
T
mb
= 25 藲C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
鹵
13
11
7.6
44
36
175
UNIT
V
V
V
A
A
A
W
藲C
1
It is not possible to make contact to pin 2 of the SOT404 or SOT428 package
September 1998
1
Rev 1.000

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