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PHB42N03LT Datasheet

  • PHB42N03LT

  • TrenchMOS transistor Logic level FET

  • 65.12KB

  • 8頁

  • PHILIPS

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Philips Semiconductors
Product specification
TrenchMOS鈩?transistor
Logic level FET
FEATURES
鈥?/div>
鈥橳rench鈥?/div>
technology
鈥?Very low on-state resistance
鈥?Fast switching
鈥?Stable off-state characteristics
鈥?High thermal cycling performance
鈥?Low thermal resistance
鈥?Surface mounting package
PHB42N03LT
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 30 V
I
D
= 42 A
g
R
DS(ON)
鈮?/div>
26 m鈩?(V
GS
= 5 V)
R
DS(ON)
鈮?/div>
23 m鈩?(V
GS
= 10 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a plastic envelope
using 鈥檛rench鈥?technology. The
device has very low on-state
resistance. It is intended for use in
dc to dc converters and general
purpose switching applications.
The PHB42N03LT is supplied in the
SOT404
surface
mounting
package.
PINNING
PIN
1
2
3
tab
gate
drain (no connection
possible)
source
drain
DESCRIPTION
SOT404
mb
2
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
鹵V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 k鈩?/div>
-
T
mb
= 25 藲C
T
mb
= 100 藲C
T
mb
= 25 藲C
T
mb
= 25 藲C
-
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
15
42
33
168
86
175
UNIT
V
V
V
A
A
A
W
藲C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
pcb mounted, minimum
footprint
TYP.
-
50
MAX.
1.75
-
UNIT
K/W
K/W
December 1997
1
Rev 1.300

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