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PHB2N50 Datasheet

  • PHB2N50

  • PowerMOS transistor

  • 61.81KB

  • 7頁(yè)

  • PHILIPS

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Philips Semiconductors
Product specification
PowerMOS transistor
PHB2N50
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope suitable for surface
mounting featuring high avalanche
energy capability, stable off-state
characteristics, fast switching and
high thermal cycling performance
with low thermal resistance. Intended
for use in Switched Mode Power
Supplies (SMPS), motor control
circuits and general purpose
switching applications.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
500
2
50
5
UNIT
V
A
W
鈩?/div>
PINNING - SOT404
PIN
1
2
3
mb
gate
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
d
g
2
1
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
I
D
I
DM
P
D
鈭哖
D
/鈭員
mb
V
GS
E
AS
I
AS
T
j
, T
stg
Continuous drain current
Pulsed drain current
Total dissipation
Linear derating factor
Gate-source voltage
Single pulse avalanche
energy
Peak avalanche current
Operating junction and
storage temperature range
CONDITIONS
T
mb
= 25 藲C; V
GS
= 10 V
T
mb
= 100 藲C; V
GS
= 10 V
T
mb
= 25 藲C
T
mb
= 25 藲C
T
mb
> 25 藲C
V
DD
鈮?/div>
50 V; starting T
j
= 25藲C; R
GS
= 50
鈩?
V
GS
= 10 V
V
DD
鈮?/div>
50 V; starting T
j
= 25藲C; R
GS
= 50
鈩?
V
GS
= 10 V
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
2
1.3
8
50
0.4
鹵
30
100
2
150
UNIT
A
A
A
W
W/K
V
mJ
A
藲C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
TYP.
-
pcb mounted, minimum
footprint
50
MAX.
2.5
-
UNIT
K/W
K/W
June 1997
1
Rev 1.000

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