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PHB21N06LT-T Datasheet

  • PHB21N06LT-T

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  • 114.87KB

  • 11頁

  • PHILIPS

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Philips Semiconductors
Product specification
N-channel TrenchMOS鈩?transistor
Logic level FET
FEATURES
鈥?/div>
鈥橳rench鈥?/div>
technology
鈥?Low on-state resistance
鈥?Fast switching
鈥?Logic level compatible
g
PHP21N06LT, PHB21N06LT
PHD21N06LT
QUICK REFERENCE DATA
d
SYMBOL
V
DSS
= 55 V
I
D
= 19 A
R
DS(ON)
鈮?/div>
75 m鈩?(V
GS
= 5 V)
R
DS(ON)
鈮?/div>
70 m鈩?(V
GS
= 10 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using 鈥檛rench鈥?technology.
Applications:-
鈥?d.c. to d.c. converters
鈥?switched mode power supplies
The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB21N06LT is supplied in the SOT404 (D
2
PAK) surface mounting package.
The PHD21N06LT is supplied in the SOT428 (DPAK) surface mounting package.
PINNING
PIN
1
2
3
tab
DESCRIPTION
gate
drain
1
source
SOT78 (TO220AB)
tab
SOT404 (D
2
PAK)
tab
SOT428 (DPAK)
tab
2
1 23
2
1
3
1
3
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Pulsed gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 藲C to 175藲C
T
j
= 25 藲C to 175藲C; R
GS
= 20 k鈩?/div>
T
j
鈮?/div>
150藲C
T
mb
= 25 藲C
T
mb
= 100 藲C
T
mb
= 25 藲C
T
mb
= 25 藲C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
鹵
15
鹵
20
19
13
76
56
175
UNIT
V
V
V
V
A
A
A
W
藲C
1
It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
August 1999
1
Rev 1.500

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