鈮?/div>
130 m鈩?(V
GS
= 10 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using 鈥檛rench鈥?technology.
Applications:-
鈥?d.c. to d.c. converters
鈥?switched mode power supplies
The PHB11N03LT is supplied in the SOT404 (D
2
PAK) surface mounting package.
The PHD11N03LT is supplied in the SOT428 (DPAK) surface mounting package.
PINNING
PIN
1
2
3
tab
gate
drain
1
source
DESCRIPTION
SOT428 (DPAK)
tab
SOT404 (D
2
PAK)
tab
2
2
3
drain
1
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Pulsed gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 藲C to 175藲C
T
j
= 25 藲C to 175藲C; R
GS
= 20 k鈩?/div>
T
mb
= 25 藲C
T
mb
= 100 藲C
T
mb
= 25 藲C
T
mb
= 25 藲C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
30
30
鹵
15
鹵
20
10.3
7.3
41
33
175
UNIT
V
V
V
V
A
A
A
W
藲C
1
It is not possible to make contact to pin 2 of the SOT404 or SOT428 package
September 1999
1
Rev 1.000
next