and PPP/IP.
broadband interface. It includes DS3/E3 framing,
mapping of ATM or PPP/HDLC. The TE3-FALC
MIB objects.
鈩?/div>
co-axial cable via transformers. Highly accurate
analog pulse shaping removes the need to measure
cable length and set the Line Build Out.
On the system side, industry standard UTOPIA and
POS-PHY interface as well as a serial clock/data port
are provided. This allows the TE3-FALC
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to be
connected to a wide array of Layer 2/3 & 4 network
processors.
B
R I E F
Applications
s
Wireless base stations
s
LAN/WAN router
s
DSLAMs
s
Remote access/concentrator
s
Multimedia gateways
Analog Line Interface
s
Single channel T3/E3 analog
receive & transmit circuitry
s
Identical T3/E3 transformer inter-
face. True software switchable
s
Clock & data recovery
s
Analog LOS detection
s
Single pulse template for all line
length 0 - 450 ft, no need for
setting of Line Build Out
Digital Jitter Attenuator
s
Two separate transmit and receive
jitter attenuators
s
Meets jitter transfer requirements
s
All line rate clocks generated
internally, no requirement for
external 34/45 MHz oscillators
s
Clock generation unit accepts
flexible frequency reference clocks,
4 MHz to 52 MHz
DS3/E3 Framer
s
E3 Framer supporting G.832,
G.751 & TBR24
s
DS3 framer supporting M23 and
C-Bit parity modes
s
Processing of all DS3 overhead
channels including the FEAC and
MDL link
s
Processing of all E3 overhead
channels such as trail trace
s
PLCP sub frame for DS3/E3 G.751
allowing the mapping of ATM cells
s
DS3/E3 BERT unit
ATM Cell Processor
s
Cell processor as per G.804
s
Mapping cells directly into DS3/E3
frames or via PLCP frame
PPP Processor
s
Bit and byte synchronous HDLC
controller
s
Generation and detection of flags,
bit stuffing, CRC-16/32
System Interfaces
s
Utopia Level 2 interface 8/16 Bit
s
POS-PHY interface 8/16 Bit
s
Serial clock and data interface
s
8/16 Bit Motorola/Intel processor
interface
TE3-FALC
Test and Diagnostic
s
JTAG test port
s
OCDS debug port
Embedded Controller
s
Embedded microcontroller with
all code & data memory
General Features
s
3.3 V I/O CMOS technology
s
1.8 V core logic supply
s
P-BGA-272 package
27 x 27 mm body size,
1.27 mm ball pitch
s
Industrial temperature range
package, -40 擄C to +85 擄C
Key Features
s
Integrated T3/E3 analog
s
Single pulse template for all line
lengths, no LBO requirement
s
Jitter attenuation in both Tx and Rx
s
Full featured DS3/E3 framer
s
ATM and PPP/HDLC mapping
s
UTOPIA or POS-PHY interface
s
Integrated 碌C running S/W driver
s
Control via 8/16 Bit Motorola/Intel
碌P i/f or inband ATM/PPP
messages
s
High level message based API
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T E 3 - F A L C
P E F 3 4 6 0 E
www.infineon.com
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N e v e r
s t o p
t h i n k i n g .
INFINEON
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