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PEEL18CV8JI-7 Datasheet

  • PEEL18CV8JI-7

  • CMOS Programmable Electrically Erasable Logic Device

  • 405.21KB

  • 10頁(yè)

  • ETC

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廬
International
CMOS
Technology
Commercial/
Industrial
PEEL鈩?18CV8 -5/-7/-10/-15/-25
CMOS Programmable Electrically Erasable Logic Device
Features
s
Multiple Speed Power, Temperature Options
- V
CC
= 5 Volts 鹵10%
- Speeds ranging from 5ns to 25 ns
- Power as low as 37mA at 25MHz
- Commercial and industrial versions available
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Development / Programmer Support
- Third party software and programmers
- ICT PLACE Development Software and PDS-3
programmer
- PLD-to-PEEL JEDEC file translator
s
Architectural Flexibility
- Enhanced architecture fits in more logic
- 74 product terms x 36 input AND array
- 10 inputs and 8 I/O pins
- 12 possible macrocell configurations
- Asynchronous clear
- Independent output enables
-- 20 Pin DIP/SOIC/TSSOP and PLCC
s
s
Application Versatility
- Replaces random logic
- Super sets PLDs (PAL, GAL, EPLD)
- Enhanced Architecture fits more logic than ordinary
PLDs
General Description
The PEEL18CV8 is a Programmable Electrically Erasable
Logic (PEEL) device providing an attractive alternative to
ordinary PLDs. The PEEL18CV8 offers the performance,
flexibility, ease of design and production practicality needed
by logic designers today.
The PEEL18CV8 is available in 20-pin DIP, PLCC, SOIC
and TSSOP packages with speeds ranging from 5ns to
25ns with power consumption as low as 37mA. EE-Repro-
grammability provides the convenience of instant repro-
gramming for development and reusable production
inventory minimizing the impact of programming changes
or errors. EE-Reprogrammability also improves factory
testability, thus assuring the highest quality possible.
The PEEL18CV8 architecture allows it to replace over 20
standard 20-pin PLDs (PAL, GAL, EPLD etc.). It also pro-
vides additional architecture features so more logic can be
put into every design. ICT鈥檚 JEDEC file translator instantly
converts to the PEEL18CV8 existing 20-pin PLDs without
the need to rework the existing design. Development and
programming support for the PEEL18CV8 is provided by
popular third-party programmers and development software.
ICT also offers free PLACE development software and a
low-cost development system (PDS-3).
Figure 1 Pin Configuration
I/CLK
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Figure 2 Block Diagram
DIP
TSSOP
PLCC
SOIC
1
04-02-004H

PEEL18CV8JI-7 產(chǎn)品屬性

  • Diodes Inc.

  • SPLD - 簡(jiǎn)單可編程邏輯器件

  • PEEL

  • 8

  • 142.8 MHz

  • 8

  • 7.5 ns

  • 5 V

  • 90 mA

  • + 85 C

  • - 40 C

  • PLCC-20

  • SMD/SMT

  • 8

  • 48

  • 5.5 V

  • 4.5 V

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