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Final Datasheet

PE3282A

1.1 GHz/510 MHz

Dual Fractional-N

PLL IC for

Frequency Synthesis

Applications

鈥?Cellular handsets

鈥?Cellular base stations

鈥?Spread-spectrum radio

鈥?Cordless phones

鈥?Pagers

Description

The PE3282A is a dual fractional-N phase-locked loop integrated circuit

designed for frequency synthesis and fabricated on Peregrine鈥檚 patented

UTSi廬 CMOS process. Each PLL includes a prescaler, phase detector, charge

pump and on-board fractional spur compensation. The 32/33 RF prescaler

(PLL1) operates up to 1.1 GHz and the

16/17 IF prescaler (PLL2) operates up to 510 MHz.

The PE3282A provides fractional-N division with power-of-two

denominator values up to 32. This allows comparison frequencies up to 32

times the channel spacing, providing a lower phase-noise floor than

integer PLLs.

Figure 1. PE3282A Block Diagram

f

in

1

f

in

1

Gnd

f

r

Gnd

6

5

7

8

9

Ref

Amp

9-Bit

Reference

Divider

21-Bit Serial Control

Interface

9-Bit

Reference

Divider

Gnd

f

in

2

f

in

2

14

16

15

16/17

Prescaler

18-Bit

Fractional-N

Main Divider

Fractional Spur

Compensation

Phase

Detector

Charge

Pump

32/33

Prescaler

19-Bit

Fractional-N

Main Divider

Features

鈥?Modulo-32 fractional-N main counters

鈥?On-board fractional spur compensation:

no tuning required, stable over

temperature

鈥?Improved phase noise compared to

integer-N architectures

鈥?Low power鈥?.5 mA at 3 V

鈥?Integrated 1.1 GHz 梅 32/33 prescaler

鈥?Integrated 510 MHz 梅 16/17 prescaler

Fractional Spur

Compensation

1

2

3

4

V

DD

V

DD

CP1

Gnd

f

o

LD

Gnd

CP2

V

DD

V

DD

Clock 11

Data

LE

12

13

Multiplexer

10

17

Phase

Detector

Charge

Pump

18

19

20

Peregrine Semiconductor Corporation

廬

6175 Nancy Ridge Drive, San Diego, CA 92121

Tel (619) 455-0660 Fax (619) 455-0770

http://www.peregrine-semi.com

Document 70/0002~07B

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