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Digitally programmable in 64 delay steps
Monotonic delay-versus-address variation
Two separate outputs: inverting & non-inverting
Precise and stable delays
Input & outputs fully TTL interfaced & buffered
10 T
2
L fan-out capability
Fits standard 24-pin DIP socket
Auto-insertable
OUT/
OUT
EN/
GND
N/C
IN
N/C
GND
N/C
N/C
EN/
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
data
3
廬
delay
devices,
inc.
PACKAGES
VCC
A0
A1
A2
VCC
N/C
N/C
N/C
VCC
A3
A4
A5
PDU16F-xx
DIP
PDU16F-xxA4
Gull-Wing
PDU16F-xxB4
J-Lead
PDU16F-xxM
Military DIP
PDU16F-xxMC4
Military Gull-Wing
FUNCTIONAL DESCRIPTION
The PDU16F-series device is a 6-bit digitally programmable delay line.
The delay, TD
A
, from the input pin (IN) to the output pins (OUT, OUT/)
depends on the address code (A5-A0) according to the following formula:
TD
A
= TD
0
+ T
INC
* A
PIN DESCRIPTIONS
IN
OUT
OUT/
A0-A5
EN/
VCC
GND
Delay Line Input
Non-inverted Output
Inverted Output
Address Bits
Output Enable
+5 Volts
Ground
where A is the address code, T
INC
is the incremental delay of the device,
and TD
0
is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The
enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state
and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced
into LOW and HIGH states, respectively. The address is not latched and must remain asserted during
normal operation.
SERIES SPECIFICATIONS
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Programmed delay tolerance:
5% or 1ns,
whichever is greater
Inherent delay (TD
0
):
9ns typical (OUT)
8ns typical (OUT/)
Setup time and propagation delay:
Address to input setup (T
AIS
):
5ns
Disable to output delay (T
DISO
):
6ns typ. (OUT)
Operating temperature:
0擄 to 70擄 C
Temperature coefficient:
100PPM/擄C (excludes TD
0
)
Supply voltage V
CC
:
5VDC
鹵
5%
Supply current:
I
CCH
= 74ma
I
CCL
= 30ma
Minimum pulse width:
10% of total delay
DASH NUMBER SPECIFICATIONS
Part
Number
PDU16F-.5
PDU16F-1
PDU16F-2
PDU16F-3
PDU16F-4
PDU16F-5
PDU16F-6
PDU16F-8
PDU16F-10
Incremental Delay
Per Step (ns)
.5
鹵
.3
1
鹵
.5
2
鹵
.5
3
鹵
1.0
4
鹵
1.0
5
鹵
1.0
6
鹵
1.0
8
鹵
1.0
10
鹵
1.5
Total Delay
Change (ns)
31.5
鹵
1.6
63
鹵
3.2
126
鹵
6.3
189
鹵
9.5
252
鹵
12.6
315
鹵
15.8
378
鹵
18.9
504
鹵
25.2
630
鹵
31.5
NOTE: Any dash number between .5 and 10 not
shown is also available.
漏
1997 Data Delay Devices
Doc #97004
1/13/97
Powered by ICminer.com Electronic-Library Service CopyRight 2003
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
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