鈥?/div>
Digitally programmable in 128 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
Input & outputs fully 10KH-ECL interfaced & buffered
Fits 48-pin DIP socket
GND
ENB
1
2
48
47
GND
OUT
data
3
廬
delay
devices,
inc.
PACKAGES
N/C
N/C
OUT
GND
ENB
N/C
N/C
N/C
GND
ENB
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
ENB
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
N/C
N/C
A2
A1
VEE
A0
N/C
A5
A4
VEE
A3
N/C
N/C
N/C
N/C
N/C
N/C
A7
VEE
A6
A0
VEE
GND
7
8
9
42
41
40
A1
A2
GND
PIN DESCRIPTIONS
IN
OUT
A0-A7
ENB
VEE
GND
Signal Input
Signal Output
Address Bits
Output Enable
-5 Volts
Ground
A3
VEE
GND
IN
15
16
17
19
34
33
32
A4
A5
GND
PDU10256H-xxC5 SMD
PDU10256H-xxMC5 Mil SMD
A6
VEE
23
24
25
A7
PDU10256H-xx DIP
PDU10256H-xxM Mil DIP
FUNCTIONAL DESCRIPTION
The PDU10256H-series device is an 8-bit digitally programmable delay line. The delay, TD
A
, from the
input pin (IN) to the output pin (OUT) depends on the address code (A7-A0) according to the following
formula:
TD
A
= TD
0
+ T
INC
* A
where A is the address code, T
INC
is the incremental delay of the device, and TD
0
is the inherent delay of
the device. The incremental delay is specified by the dash number of the device and can range from
0.5ns through 10ns, inclusively. The enable pin (ENB) is held LOW during normal operation. When this
signal is brought HIGH, OUT is forced into a LOW state. The address is not latched and must remain
asserted during normal operation.
SERIES SPECIFICATIONS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Total programmed delay tolerance:
5% or 2ns,
whichever is greater
Inherent delay (TD
0
):
12ns typical
Setup time and propagation delay:
Address to input setup (T
AIS
):
3.6ns
Disable to output delay (T
DISO
):
1.7ns typical
Operating temperature:
0擄 to 70擄 C
Temperature coefficient:
100PPM/擄C (excludes TD
0
)
Supply voltage V
EE
:
-5VDC
鹵
5%
Power Dissipation:
925mw typical (no load)
Minimum pulse width:
16% of total delay
DASH NUMBER SPECIFICATIONS
Part
Number
PDU10256H-.5
PDU10256H-1
PDU10256H-2
PDU10256H-3
PDU10256H-4
PDU10256H-5
PDU10256H-6
PDU10256H-8
PDU10256H-10
Incremental Delay
Per Step (ns)
0.5
鹵
0.3
1.0
鹵
0.5
2.0
鹵
0.5
3.0
鹵
1.0
4.0
鹵
1.0
5.0
鹵
1.5
6.0
鹵
1.5
8.0
鹵
2.0
10.0
鹵
2.0
Total
Delay (ns)
127.5
鹵
6.4
255
鹵
12.8
510
鹵
25.5
765
鹵
38.2
1020
鹵
51.0
1275
鹵
63.8
1530
鹵
76.5
2040
鹵
102
2550
鹵
128
漏
1997 Data Delay Devices
NOTE: Any dash number between .5 and 10
not shown is also available.
Doc #97047
12/17/97
Powered by ICminer.com Electronic-Library Service CopyRight 2003
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
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