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PDC2 Datasheet

  • PDC2

  • Controller Miscellaneous - Datasheet Reference

  • 25頁

  • ETC

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Features
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Compatible with an Embedded ARM7TDMI
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Processor
Generates Transfers to/from Serial Peripherals Such as UART, USART, SSC and SPI
Supports Up to 12 Peripherals 鈥?Parameterizable on Request
One ARM
廬
Cycle Needed for a Transfer from Memory to Peripheral
Two ARM Cycles Needed for a Transfer from Peripheral to Memory
Fully Scan Testable up to 98% Fault Coverage
Can be Directly Connected to the Atmel Implementation of the AMBA
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Bridge
Not Fully Compatible with AMBA: Retract Response not Supported
Description
The Peripheral Data Controller 2 (PDC2) transfers data between on-chip peripherals
such as the UART, USART, SSC and SPI and the on- and off-chip memories. This
transfer is achieved via the AMBA Bridge using a simple arbitration mechanism
between the AMBA System Bus (ASB) and the PDC2 to control Bridge access. This
avoids processor intervention and removes the processor interrupt handling overhead.
This significantly reduces the number of clock cycles required for a data transfer and,
as a result, improves the performance of the microcontroller and makes it more power-
efficient.
The PDC2 channels are implemented in pairs, each pair being dedicated to a particu-
lar peripheral. One PDC2 channel in the pair is dedicated to the receiving channel and
one to the transmitting channel of each UART, USART, SSC and SPI.
The user interface of a PDC2 channel is integrated in the memory space of each
peripheral. It contains a 32-bit memory pointer register and a 16-bit transfer count reg-
ister plus a 32-bit register for next memory pointer and a 16-bit register for next
transfer count. The peripheral triggers PDC2 transfers using transmit and receive sig-
nals. When the programmed data is transferred, an end of transfer interrupt is
generated by the corresponding peripheral.
32-bit
Embedded ASIC
Core Peripheral
Peripheral Data
Controller 2
(PDC2)
Rev. 1734B鈥揅ASIC鈥?2/02
1

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