PC87550 PicoPower North Bridge鈥擯CI System Controller
PRELIMINARY
February 1997
PC87550
PicoPower North Bridge鈥擯CI System Controller
General Description
A high-performance, highly integrated system controller for
Microsoft
廬
Windows
廬
-compatible computers, the PC87550
signi鏗乧antly improves upon the performance offered by cur-
rent system-logic solutions. The PCI-based system control-
ler is optimized for portable multimedia systems with critical
form-factor and power consumption requirements.
The PC87550 supports full PCI, DRAM, CPU, and L2-cache
concurrency. It achieves a more effective utilization of the
CPU bus by allowing the CPU execution to continue while
the PCI Master is accessing the DRAM.
The presence of two independent write buffers improves per-
formance by allowing PCI memory writes and DRAM
memory writes/reads to occur concurrently. The PC87550
also supports the concurrent operation of an external PCI
Master and a Pentium processor.
The PC87550 supports sustained PCI bursting of up to 120
Mbytes per second. It can achieve a sustained burst rate of
x-1-1-1-1.... for both CPU-to-PCI and PCI Master-to-DRAM
accesses.
The PC87550 system controller integrates the following
functions in a single 388-pin BGA package:
tling to efficiently control the power consumption and heat
dissipation associated with the processor. An innovative pro-
gramming model simpli鏗乪s the BIOS development task with-
out compromising any of the power management features.
The PC87550 provides a 32- or 64-bit data path between the
CPU and the main memory; a 32-bit data path between the
CPU bus and the PCI Local bus; and a 32-bit data path be-
tween the PCI Local bus and the main memory.
PC87560 PCI system I/O controller complements the
PC87550 solution by providing a highly integrated bridge be-
tween the PCI and ISA buses. Both devices contain the nec-
essary logic to support master and slave cycles on both PCI
and ISA buses.
To enable a full-featured docking station design, the
PC87550 provides all the hooks required to support PCI hot-
warm-, and cold-docking. It is fully optimized to work with
PC87560 and the NILE II devices to support a full secondary
ISA bus in the PCI docking station, thus allowing PCI and
ISA slots in the docking station. The PC87550 also imple-
ments the docking interface control logic to enable port rep-
licator dock and PCI hot-, warm-, and cold-docking. This in-
terface provides a seamless support for docking without
requiring external logic.
To enable a full-featured docking station design, the
PC87550 provides all the hooks required to support PCI hot-
warm-, and cold-docking. It is fully optimized to work with
PC87560 and the NILE II devices to support a full secondary
ISA bus in the PCI docking station, thus allowing PCI and
ISA slots in the docking station. The PC87550 also imple-
ments the docking interface control logic to enable port rep-
licator dock and PCI hot-, warm-, and cold-docking. This in-
terface provides a seamless support for docking without
requiring external logic.
The 388-pin BGA packaging offers a sleek, durable package
with good thermal properties and noise immunity. The device
comes with full technical and hardware support, including
samples, evaluation boards, and design examples.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
CPU-to-PCI bus interface controller/arbiter
L2-cache controller
DRAM controller
Power management controller
Data path controller
SmartDock
鈩?/div>
and SmartDock-II hot-docking interface
The level-2 cache controller supports synchronous burst,
and pipelined synchronous SRAM.
It supports cache sizes ranging from 256 Kbytes to 512
Kbytes. Additionally, buffered write-through cache update
schemes allow further performance gains by not stalling the
CPU on L1 writeback cycles.
A sophisticated DRAM controller supports leading-edge 3.3V
DRAM technologies. Support for synchronous DRAM allows
the PC87550 to achieve improved performance in a cache-
less system con鏗乬uration. The DRAM controller implements
the logic required to use high-speed DRAM, reducing the
performance overhead of the L2-cache miss cycles. It pro-
vides a synchronous interface between the CPU and PCI
buses to exploit the maximum potential of the PCI band-
width.
Active and passive power management features enable sys-
tems with superior power and thermal management.
PC87550 supports both legacy and Advanced Con鏗乬uration
and Power management Interface (ACPI) implementations.
A special thermal control mechanism uses CPU clock throt-
Intel
廬
is a registered trademark of Intel Corporation.
Pentium
廬
is a registered trademark of Intel Corporation.
Microsoft
廬
is a registered trademark of Microsoft Corporation.
Windows
廬
is a registered trademark of Microsoft Corporation.
AMD
廬
is a registered trademark of Advanced Micro Devices, Inc.
Cyrix
廬
is a registered trademark of
SmartDock
鈩?/div>
is a trademark of
Features
n
Optimized single-chip PCI system controller for Intel
廬
Pentium
廬
processors
鈥?Processor bus speeds of 50-, 60-, and 66-MHz
鈥?Supports 5-class processors from AMD
廬
and Cyrix
廬
鈥?Supports processors with 3.2V or 2.5V CPU bus
interface
鈥?Supports level-1 write-back or write-through cache
鈥?Supports both toggle and linear burst sequences
鈥?Supports CPU address pipelining
鈥?Optimized for Multimedia Extension (MMX)
processors
漏 1997 National Semiconductor Corporation
ds012937
http:\\www.national.com
1
PrintDate=1997/02/08 PrintTime=10:42:59 ds012937 Rev. No. 5
Final
1
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