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PC87310 Datasheet

  • PC87310

  • PC87310 (SuperI/OTM) Dual UART with Floppy Disk Controller a...

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PC87310 (SuperI O) Dual UART with Floppy Disk Controller and Parallel Port
August 1990
PC87310 (SuperI O
TM
)
Dual UART with Floppy Disk Controller
and Parallel Port
General Description
The PC87310 incorporates two full function UARTs a flop-
py disk controller (FDC) with analog data separator one
parallel port game port decode hard disk controller de-
code standard XT AT address decoding for on-chip func-
tions and a Configuration Register in one chip Thus it of-
fers a single chip solution to the most commonly used
IBM PC XT and AT peripherals The floppy disk controller
is fully compatible with the industry standard 765 architec-
ture but it includes many more advanced options such as a
high performance data separator extended track range to
4096 implied seek command scan command and both
standard IBM formats as well as ISO 3 5 formats The
UARTs are compatible with either the INS8250N-B or the
NS16450 The parallel port hard disk select and game port
select logic maintain complete compatibility with the IBM XT
and AT Hardware selects XT or AT compatibility
The Configuration Register is one byte wide and can be
programmed via hardware or software Through its control
the user can assign standard AT addresses and disable any
major on-chip function (e g the FDC either UART or the
parallel port) independently of the others This allows for
flexibility in system configuration when adapter cards con-
tain duplicate functions
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Features
Y
Y
Y
Y
Y
Y
100% compatible to the IBM PC XT and AT
architectures
Software compatible to the INS8250N-B INS8250A and
NS16450 UARTs
100% compatible to the industry standard 765A
architecture
On-chip analog data separator operates up to 1 Mb s
Implements all DP8473 Floppy Disk Controller functions
Bidirectional parallel port for printer or scanner opera-
tion Provides all standard Centronics and IBM PC XT
and AT interface signals
Y
Y
Y
Y
Y
Decoding and chip selects for an IDE hard disk
interface
Address decoding and strobe generation for a game
port
Fabricated in NSC鈥檚 1 5
m
M2CMOS process
Low power CMOS with a power down mode
100-pin EIAJ plastic flatpak package
Integrates all PC-XT PC-AT logic
On chip 24 MHz crystal oscillator
DMA enable logic
IBM compatible address decode of A0 鈥?A9
24 mA
mP
bus interface buffers
40 mA floppy drive interface buffers
Data rate and drive control registers
Precision analog data separator
Self-calibrating PLL and delay line
Automatically chooses one of three filters
Intelligent read algorithm
Two pin programmable precompensation modes
Other enhancements
Implied seek up to 4000 tracks
IBM or ISO formatting
Separate interrupt request lines for the parallel and se-
rial ports
Adds or deletes standard asynchronous communication
bits (start parity and stop) to or from the serial data
Independently controlled transmit receive line status
and data set interrupts
Programmable baud generators for each UART channel
divide the input clock by 1 to (2
16
b
1) and generate
the internal 16
c
sample clock
MODEM control functions for each UART channel
(CTS RTS DSR DTR RI and DCD)
Fully programmable serial-interface characteristics
5 6 7 or 8 bit characters
Even odd or no parity generation and detection
1 1
or 2 stop bit generation
High current drive capability for the parallel port
Note
This part is patented
TRI-STATE is a registered trademark of National Semiconductor Corporation
Plus-2
TM
and SuperI O
TM
are trademarks of National Semiconductor Corporation
IBM PC-XT PC-AT and PS 2 are registered trademarks of International Business Machines Corporation
C
1995 National Semiconductor Corporation
TL C 10591
RRD-B30M65 Printed in U S A

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