Description.
intended for use in GSM terminals. It delivers 35 dBm at 900 MHz with 55 % power added
鈩?/div>
unbalanced load using a single 3.5 V supply.
The circuit has an analog ramp signal to control output power level and a logical on/
off signal for power down mode. It can be used in dual-band amplifiers using the band
select logical signal. It can be operated up to 50 % duty cycle with minimum performance
degradation. The circuit is housed in a specially designed QSOP16 (150 mil body)
package and the implementation requires only few external components.
25 GHz f
t
state-of-the-art deep trench isolated double-poly silicon bipolar process
with additional features for improved wireless performance has been used. On-chip
capacitors and inductors are used for the integrated internal matching network. Special
front-side metallized substrate contacts provide excellent ground paths from active
devices to the highly doped semiconductor substrate and package ground.
Key features.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
2.7 to 5.0 V single supply operation
35 dBm output power at 3.5 V
55 % Power Added Efficiency
Input matched to 50
鈩?/div>
Complete on chip input and
interstage matching
Analog power control
Less than 10
碌A(chǔ)
current
consumption in power down mode
Proven RF Silicon Technology
Reliability
Minimum number of external
components for low overall solution
cost
鈥?/div>
鈥?/div>
鈥?/div>
V
CC
鈥?/div>
RFin
RFout
B
SEL
Power
Control
BIAS
TX - ON
L
PB
10
03
4
Figure 1. Block diagram.
Figure 2. Package outlook.
1
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