鈥?/div>
DIP, LCC, and PLCC available
鈥?5 ns commercial version
4 ns t
CO
3 ns t
S
5 ns t
PD
181-MHz state machine
鈥?10 ns military and industrial versions
7 ns t
CO
6 ns t
S
10 ns t
PD
110-MHz state machine
鈥?15-ns commercial, industrial, and military versions
鈥?25-ns commercial, industrial, and military versions
鈥?/div>
High reliability
鈥?Proven Flash EPROM technology
鈥?100% programming and functional testing
Functional Description
The Cypress PALCE22V10 is a CMOS Flash Erasable sec-
ond-generation programmable array logic device. It is imple-
mented with the familiar sum-of-products (AND-OR) logic
structure and the programmable macrocell.
Logic Block Diagram (PDIP/CDIP)
V
SS
12
I
11
I
10
I
9
I
8
I
7
I
6
I
5
I
4
I
3
I
2
CP/I
1
PROGRAMMABLE
AND ARRAY
(132 X 44)
8
10
12
14
16
16
14
12
10
8
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Preset
13
I
14
I/O9
15
I/O8
16
I/O 7
17
I/O6
18
I/O5
19
I/O4
20
I/O3
21
I/O2
22
I/O1
23
I/O0
24
V
CC
CE22V10鈥?
Pin Configuration
I
I
CP/I
NC
V
CC
I/O0
I/O1
4 3 2 1 282726
I
I
I
NC
I
I
I
5
6
7
8
9
10
11
12131415161718
V
SS
NC
I/O9
I/O8
CE22V10鈥?
25
24
23
22
21
20
19
I/O 2
I/O 3
I/O 4
N/C
I/O 5
I/O 6
I/O 7
I
I
I
NC
I
I
I
5
6
7
8
9
10
11
I
I
CP/I
NC
V
CC
I/O0
I/O1
4 3 2 1 2827 26
25
24
23
22
21
20
19
I/O 2
I/O 3
I/O 4
N/C
I/O 5
I/O 6
I/O 7
CE22V10鈥?
121314 1516 1718
V
SS
NC
LCC
Top View
PLCC
Top View
PAL is a registered trademark of Advanced Micro Devices.
Cypress Semiconductor Corporation
Document #: 38-03027 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
I/O9
I/O8
I
I
I
I
I
I
鈥?/div>
CA 95134 鈥?408-943-2600
Revised September 1996
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