This is an abbreviated data sheet. Contact a Cypress
representative for complete specifications.
鈥?55 mA max. 鈥淟鈥?/div>
鈥?90 mA max. standard
鈥?120 mA max. military
鈥?CMOS EPROM technology for reprogrammability
鈥?Variable product terms
鈥?2 x (8 through 16) product terms
鈥?User-programmable macrocell
鈥?Output polarity control
鈥?Individually selectable for registered or
combinatorial operation
鈥?20, 25, 35 ns commercial and industrial
鈥?25, 30, 40 ns military
鈥?Up to 22 input terms and 10 outputs
鈥?High reliability
鈥?Proven EPROM technology
鈥?100% programming and functional testing
鈥?Windowed DIP, windowed LCC, DIP, LCC, and PLCC
available
Functional Description
The Cypress PALC22V10 is a CMOS second-generation
programmable logic array device. It is implemented with the
familiar sum-of-products (AND-OR) logic structure and a
new concept, the 鈥減rogrammable macrocell.鈥?/div>
Logic Block Diagram (PDIP/CDIP)
VSS
12
I
11
I
10
I
9
I
8
I
7
I
6
I
5
I
4
I
3
I
2
CP/I
1
PROGRAMMABLE
AND ARRAY
(132 X 44)
8
10
12
14
16
16
14
12
10
8
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Preset
13
I
14
I/O9
15
I/O8
16
I/O 7
17
I/O6
18
I/O5
19
I/O4
20
I/O3
21
I/O2
22
I/O1
23
I/O0
24
VCC
Pin Configuration
LCC/PLCC
Top View
I
I
CP/I
NC
VCC
I/O 0
I/O 1
4 3 2 1 282726
5
I
6
I
I
NC 7
8
9
I
10
I
11
I
12131415161718
I/O 9
I/O 8
VSS
NC
I
I
I
25
24
23
22
21
20
19
I/O 2
I/O 3
I/O 4
NC
I/O 5
I/O 6
I/O 7
Cypress Semiconductor Corporation
Document #: 38-03052 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised April 9, 2004
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