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P89LPC931 Datasheet

  • P89LPC931

  • 8-bit microcontrollers with two-clock 80C51 core 4 kB/8 kB 3...

  • 928.32KB

  • 54頁

  • ETC

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P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
4 kB/8 kB 3 V Flash with 256-byte data RAM
Rev. 03 鈥?06 October 2003
Product data
1. General description
The P89LPC930/931 is a single-chip microcontroller designed for applications
demanding high-integration, low cost solutions over a wide range of performance
requirements. The P89LPC930/931 is based on a high performance processor
architecture that executes instructions in two to four clocks, six times the rate of
standard 80C51 devices. Many system-level functions have been incorporated into
the P89LPC930/931 in order to reduce component count, board space, and system
cost.
2. Features
s
A high performance 80C51 CPU provides instruction cycle times of 167-333 ns for
all instructions except multiply and divide when executing at 12 MHz. This is
6 times the performance of the standard 80C51 running at the same clock
frequency. A lower clock frequency for the same performance results in power
savings and reduced EMI.
s
2.4 V to 3.6 V V
DD
operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
s
4 kB/8 kB Flash code memory with 1 kB sectors, and 64-byte page size.
s
Byte-erase allowing code memory to be used for data storage.
s
Flash program operation completes in 2 ms.
s
Flash erase operation completes in 2 ms.
s
256-byte RAM data memory.
s
Two 16-bit counter/timers. Each timer may be con鏗乬ured to toggle a port output
upon timer over鏗俹w or to become a PWM output.
s
Real-Time clock that can also be used as a system timer.
s
Two analog comparators with selectable inputs and reference source.
s
Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities.
s
400 kHz byte-wide I
2
C-bus communication port.
s
SPI communication port.
s
Eight keypad interrupt inputs, plus two additional external interrupt inputs.
s
Four interrupt priority levels.
s
Watchdog timer with separate on-chip oscillator, requiring no external
components. The Watchdog time-out time is selectable from 8 values.
s
Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available.

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