鈥?/div>
PIN CONFIGURATION
VDD
XIN
XOUT/50MHz_OE*^
GND
VDD
50MHz/FS0*^
GND
50MHz/FS1*^
50MHz/FS2*
T
FS3
T
50MHz/SS0*
T
VDD
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
VDD
25MHz/100MHz
GND
SDRAMx2
GND
SDRAMx2
VDD
VDD
25MHz/125MHz
GND
25MHz/125MHz
Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
Advanced, low power, sub-micron CMOS processes.
25MHz fundamental crystal or clock input.
4 outputs at 50MHz, 2 outputs selectable at 25MHz or
125MHz, 1 output selectable at 25MHz or 100MHz.
2 SDRAM selectable frequencies of 66.6, 75, 83.3,
100MHz (Double Drive Strength).
All non SDRAM outputs can be disabled (tri-state)
Spread spectrum technology selectable for EMI
reduction from
鹵0.5%, 鹵0.75%
for SDRAM and 100MHz
output.
Zero PPM synthesis error in all clocks.
Ideal for Network switches.
3.3V operation.
Available in 24-Pin 150mil SSOP
.
Note:
SDRAMx2: Double Drive strength.
T
: Tri-Level input
^
: Internal pull-up
resistor. *: Bi-directional pin (input value is latched upon power-up).
PLL650-02
DESCRIPTIONS
The PLL 650-02 is a low cost, low jitter, and high
performance clock synthesizer. With PhaseLink鈥檚
proprietary analog Phase Locked Loop techniques, the chip
accepts 25 MHz crystal, and produces multiple output
clocks for networking chips, PCI devices, SDRAM, and
ASICs, with double drive strength for its SDRAM outputs.
FREQUENCY TABLE
FS1
0
0
1
1
FS0
0
1
0
1
SDRAM
100MHz
SST
75MHz
S ST
83.3MHz
SST
66.6MHz
SST
FS3
0
M
1
Pin 13, 15
Disable
125MHz
25MHz
FS2
0
M
1
Pin 22
25MHz
Disable
100MHz
SST
FS(2:3): Tri-level inputs.
SST: SST modulation applied (see selection table)
BLOCK DIAGRAM
4
XIN
XOUT
XTAL
OSC
50MHz
(can be disabled)
25MHz/125MHz
(can be disabled)
SDRAM (66.6, 75, 83.3, 100MHz)
2
Control
Logic
FS (0:3)
2
1
25MHz/100MHz
(can be disabled)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 1
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