鈥?/div>
19MHz to 65MHz crystal input.
Output range: 9.5MHz 鈥?65MHz
Selectable OE Logic (enable high or enable low).
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Supports 2.5V or 3.3V Power Supply.
Available in die form.
DIE CONFIGURATION
OUTSEL0^
65 mil
OUTSEL1^
Reserved
VDD
VDD
VDD
VDD
N/C
(1550,1475)
17
16
25
24
23
22
21
20
19
18
GNDBUF
CMOS
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
OE_SEL^
XIN
XOUT
N/C
62 mil
26
27
Die ID:
A2020-20B
15
28
14
DESCRIPTION
The PLL620-80 is a XO IC specifically designed to
work with fundamental or 3
rd
OT crystals between
19MHz and 65MHz. The selectable divide by two
feature extends the operation range from 9.5MHz to
65MHz. It requires very low current into the crystal
resulting in better overall stability. The OE logic
feature allows selection of enable high or enable low.
Furthermore, it provides selectable CMOS, PECL or
LVDS outputs.
S2^
OE
CTRL
N/C
13
29
12
11
30
C502A
31
1
2
3
4
5
6
7
8
10
9
Reserved
Y
(0,0)
X
OUTPUT SELECTION AND ENABLE
OUT_SEL1*
(Pad 18)
0
0
1
1
OE_SELECT
(Pad 9)
0
1 (Default)
OUT_SEL0*
(Pad 25)
0
1
0
1
OE_CTRL
(Pad 30)
0
1 (Default)
0 (Default)
1
Selected Output*
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
State
Tri-state
Output enabled
Output enabled
Tri-state
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
OE
Q
XIN
XOUT
Oscillator
Amplifier
Q
S2
PLL620-80
Pads #9, #18 & #25: Bond to GND to set to 鈥?鈥?
No connection results to 鈥渄efault鈥?setting
through internal pull-up.
OE_CTRL: Logical states defined by PECL levels if OE_SELECT is 鈥?鈥?/div>
Logical states defined by CMOS levels if OE_SELECT is 鈥?鈥?/div>
OUTPUT FREQUENCY SELECTOR
S2
0
1(Default)*
*Internally set to 鈥楧efault鈥?through 60K
Output
Input/2
Input
pull-up resistor
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/09/04 Page 1
GNDBUF
GNDBUF
GND
GND
GND
GND
GND
1
2
3
4
5
6
7
