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P620-30DC Datasheet

  • P620-30DC

  • PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)

  • 6頁

  • PLL

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PLL620-30
PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
65MHz to 130MHz Crystal input.
Output range: 32.5MHz 鈥?130MHz (no PLL).
Low Injection Power for crystal, 50uW.
Complementary outputs: PECL or LVDS.
Selectable OE Logic
Supports 2.5V or 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
62 mil
DIE CONFIGURATION
65 mil
Reserved
Reserved
OESEL^
VDD
VDD
VDD
VDD
N/C
(1550,1475)
17
16
25
24
23
22
21
20
19
18
GNDBUF
N/C
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
OUTSEL^
XIN
XOUT
N/C
S2^
OE
CTRL
N/C
26
27
Die ID:
A2020-20A
15
28
14
DESCRIPTION
The PLL620-30 is a XO IC specifically designed to
drive fundamental or 3
rd
OT crystals from 65MHz to
130MHz, with selectable PECL or LVDS outputs and
OE logic (enable high or enable low). Its design was
optimized to tolerate higher limits of interelectrode
capacitance and bonding capacitance to improve
yield. It achieves very low current into the crystal
resulting in better overall stability.
13
29
12
11
30
C502A
31
1
2
3
4
5
6
7
8
10
9
Reserved
Y
(0,0)
X
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
OUTPUT SELECTION AND ENABLE
OUTSEL
(Pad #9)
0
1
Selected Output
LVDS
PECL (default)
OESEL
(Pad #25)
0
1 (default)
BLOCK DIAGRAM
OE
Q
XIN
XOUT
Oscillator
Amplifier
OE_CTRL
(Pad #30)
0
1
0
1
State
Tri-state
Output enabled (default)
Output enabled (default)
Tri-state
Pad #9, #25: Bond to GND to set to 鈥?鈥? Internal pull up.
Pad #30: Logical states defined by PECL levels if OESEL is 鈥?鈥?/div>
Logical states defined by CMOS levels if OESEL is 鈥?鈥?/div>
Q
OUTPUT FREQUENCY SELECTOR
PLL620-30
S2
0
1(Default)*
*Internally set to 鈥楧efault鈥?through 60K
Output
Input/2
Input
pull-up resistor
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/09/04 Page 1
GNDBUF
GNDBUF
GND
GND
GND
GND
GND

P620-30DC相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    Low Phase Noise XO with multipliers (for HF Fund. and 3rd O....
    PLL
  • 英文版
    Low Phase Noise XO with multipliers (for 100-200MHz Fund or ...
    PhaseLink Corpo...
  • 英文版
    Low Phase Noise XO with multipliers (for 100-200MHz Fund or ...
    PLL
  • 英文版
    Low Phase Noise XO with multipliers (for 100-200MHz Fund or ...
    PhaseLink Corpo...
  • 英文版
    Low Phase Noise XO with multipliers (for 100-200MHz Fund or ...
    PLL
  • 英文版
    Low Phase Noise XO with multipliers (for 100-200MHz Fund or ...
    PhaseLink Corpo...
  • 英文版
    Low Phase Noise XO with multipliers (for 100-200MHz Fund or ...
    PhaseLink Corpo...
  • 英文版
    Low Phase Noise XO with multipliers (for 100-200MHz Fund or ...
    PLL
  • 英文版
    Low Phase Noise XO with multipliers (for 100-200MHz Fund or ...
    PhaseLink Corpo...
  • 英文版
    Low Phase Noise XO with multipliers (for 100-200MHz Fund or ...
    PhaseLink Corpo...
  • 英文版
    Low Phase Noise XO with multipliers (for 100-200MHz Fund or ...
    PLL
  • 英文版
    Low Phase Noise XO (for HF Fund. and 3-rd O.T.)
    PLL
  • 英文版
    PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)
    PLL
  • 英文版
    Low Phase Noise XO (9.5-65MHz Output)
    PLL
  • 英文版
    Low Phase Noise XO (9.5-65MHz Output)
    PhaseLink Corpo...
  • 英文版
    Low Phase Noise XO with multipliers (for 100-200MHz Fund or ...
    PhaseLink Corpo...
  • 英文版
    Low Phase Noise XO with multipliers (for 100-200MHz Fund or ...
    PLL
  • 英文版
    Low Phase Noise XO with multipliers (for 100-200MHz Fund or ...
    PLL
  • 英文版
    Low Phase Noise XO with multipliers (for 100-200MHz Fund or ...
    PhaseLink Corpo...
  • 英文版
    Low Phase Noise XO with multipliers (for 100-200MHz Fund or ...
    PLL

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