鈥?/div>
Integrated crystal oscillator circuitry (XO).
Low phase noise (-135dBc @ 10kHz offset)
selectable frequency multipliers (x1, x2, x4, x8
as bonding options).
3.3V supply voltage.
Uses inexpensive fundamental-mode parallel
resonant crystals (from 12 to 25MHz).
Selectable High Drive (30mA) or Standard Drive
(10mA) output.
Available in DIE (65 mil x 62 mil).
DIE CONFIGURATION
65 mil
VDD
VDD
OE^
S0
V
S1
V
S2
V
(1550,1475)
25
23
21
20
19
18
Die ID:
A0303-03H
XIN
27
62 mil
13
CLK
XOUT
29
DESCRIPTION
The PLL602-00 is a monolithic low jitter and low
phase noise (-135dBc @10kHz offset), high
performance CMOS XO IC. This flexible device can
be used as a XO with output frequencies ranging
from F
XIN
x 1 to F
XIN
x 8 thanks to selector pads
allowing bonding options (see Divider Selection
Table on this page). This makes the PLL602-00 ideal
for a wide range of applications from 12MHz to
200MHz (including 50MHz, 77.76MHz, 125MHz and
155.52MHz, etc.).
Y
X
(0,0)
C502A
7
10
GND
Note:
^ denotes internal pull up
V
denotes internal pull down
MULTIPLIER SELECTION
SELECTION
S2
S1
S0
0
0
0
0
0
1
0
1
0
1
0
0
0
1
1
1
1
0
1
0
1
1
1
1
F
XIN
CLK (MHz)
F
XIN
x 2
F
XIN
x 4
F
XIN
x 1
F
XIN
x 8
F
XIN
x 2*
F
XIN
x 4*
F
XIN
x 1*
F
XIN
x 8*
BLOCK DIAGRAM
S[0:2]
12MHz 鈥?25MHz
XIn
XO
XOut
Selectable
PLL
CLK
Note: -
Selector pads default to 鈥?鈥? wire bond to VDD to set to 鈥?鈥?/div>
- (*) High-drive CMOS output
PAD DESCRIPTION
Name
Number
Description
XIN
27
29
7,10
13
18,19,20
21,22,23
25
Crystal input connection.
Crystal connection.
Ground.
Clock Output.
Frequency selection pad
3.3V Power Supply.
Output Enable: 鈥?鈥?to disable (tri-
state output), 1鈥?(default value
when not connected) to enabled
the output.
DIE SPECIFICATIONS
Name
Value
XOUT
GND
CLK
S[0:2]
VDD
OE
Size
Reverse side
Pad dimensions
Thickness
62 x 65 mil
GND
80 micron x 80 micron
10 mil
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 1
GND
1
2
3
4
