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Available in 8-Pin SOIC GREEN/RoHS compliant
Package.
PACKAGE PIN CONFIGURATION
XIN/FIN
VDD
GND
27MHz
1
2
3
4
8
7
6
5
XOUT
FSEL^
DNC
ACLK
Note:
^: Internal pull-up resistor. The internal pull-up resistor
results in a default high value when no pull-down resistor is
connected to this pin.
PLL601-26
DESCRIPTION
The PLL601-26 is a low cost integrated XO IC
designed to work with a fundamental 27MHz crystal
or a clock input. In addition to a 27MHz clock
reference output, it provides two selectable audio
frequencies (12.288MHz, and 24.576MHz), making
the chip ideal for handheld, STB and MPEG Video
applications. Additional system frequencies can also
be supported by cascading the PLL601-26 with
PhaseLink鈥檚 QTC programmable clock family.
AUDIO CLOCK SELECTION
FSEL
0
1(Default)
ACLK (MHz)
12.288
24.576
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/28/05 Page 1