鈥?/div>
Low phase noise XO
Input from crystal or clock at 10-27MHz.
Integrated crystal load capacitor: no external
load capacitor required.
Output clocks up to 160MHz.
Low phase noise (-125dBc/Hz @ 1kHz).
Output Enable function.
Low jitter (RMS): 6.4ps (period), 9.4ps (accum.)
Advanced low power sub-micron CMOS process.
3.3V operation.
Available in 16-Pin SOIC or TSSOP.
PIN CONFIGURATION
CLK
REFEN
VDD
VDD
VDD
XOUT
S1^
XIN
1
2
16
15
GND
GND
GND
REFOUT
OE^
S0^
S2^
GND
PLL 601-02
3
4
5
6
7
8
14
13
12
11
10
9
DESCRIPTION
The PLL601-02 is a low cost, high performance and
low phase noise clock synthesizer with 4x or 8x mul-
tiplier. Using PhaseLink鈥檚 proprietary analog and
digital Phase Locked Loop techniques, this IC can
produce up to a 160MHz out put. Ideal for
155.52MHz applications.
MULTIPLIER SELECT TABLE
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
CLK
Test
Reserved
4x Input (Low Frequency VCO*)
8x Input (Low Frequency VCO*)
Reserved
XO Frequency Pass through
4x Input (High Frequency VCO*)
8x Input (High Frequency VCO*)
*: Low Frequency VCO is advised for best performance at 155.52MHz
BLOCK DIAGRAM
S2
S1
S0
ROM Based
Multipliers
VCO
Divider
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLK
OE
XIN
XOUT
XTAL
OSC
REFEN
REFOUT
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 1
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