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P601-01SC Datasheet

  • P601-01SC

  • Low Phase Noise PLL Clock Multiplier

  • 5頁

  • PLL

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PLL601-01
Low Phase Noise PLL Clock Multiplier
FEATURES
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Low phase noise XO
Input from crystal or clock at 10-27MHz.
Integrated crystal load capacitor: no external
load capacitor required.
Output clocks up to 160MHz.
Low phase noise (-125dBc/Hz @ 1kHz).
Output Enable function.
Low jitter (RMS): 7.2ps (period), 11.2ps (accum.)
Advanced low power sub-micron CMOS process.
3.3V operation.
Available in 16-Pin SOIC or TSSOP.
PIN CONFIGURATION
CLK
REFEN
VDD
VDD
VDD
XOUT
S1^
XIN
1
2
16
15
GND
GND
GND
REFOUT
OE^
S0^
S3^
S2^
PLL 601-01
3
4
5
6
7
8
14
13
12
11
10
9
DESCRIPTION
Note: ^ denotes internal pull up.
The PLL601-01 is a low cost, high performance and
low phase noise clock synthesizer. Using Phase-
Link鈥檚 proprietary analog and digital Phase Locked
Loop techniques, this IC can produce up to a
160MHz output.
BLOCK DIAGRAM
S3
S2
S1
S0
ROM Based
Multipliers
VCO
Divider
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLK
OE
XIN
XOUT
XTAL
OSC
REFEN
REFOUT
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 1

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