PDF預(yù)覽

• 1
• 2
• 3
• 4
• 5
• 6
• 7
• 8
• 9
• 10

3Q0

FS

VCCQ

REF

GND

TEST

2F1

VCCN

FB

VCCN

2Q1

2Q0

3Q1

3Q0

21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321

21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321

PI6C3Q991, PI6C3Q993

3.3V Programmable Skew PLL Clock Driver

SuperClock

廬

Description

Features

聲 PI6C3Q99X family provides following products:

PI6C3Q991: 32-pin PLCC version

PI6C3Q993: 28-pin QSOP version

聲 Inputs are 5V I/O Tolerant

聲 4 pairs of programmable skew outputs

聲 Low skew: 200ps same pair; 250ps all outputs

聲 Selectable positive or negative edge synchronization:

Excellent for DSP applications

聲 Synchronous output enable

聲 Output frequency: 3.75 MHz to 85 MHz

聲 2x, 4x, 1/2, and 1/4 outputs

聲 3 skew grades:

聲 3-level inputs for skew and PLL range control

聲 PLL bypass for DC testing

聲 External feedback, internal loop filter

聲 12mA balanced drive outputs

聲 Low Jitter: < 200ps peak-to-peak

聲 Industrial temperature range

聲 Pin-to-pin compatible with IDT QS5V991 and QS5V993

聲 Available in 32-pin PLCC and 28-pin QSOP

The PI6C3Q99X family is a high fanout 3.3V PLL-based clock driver

intended for high performance computing and data-communica-

tions applications. A key feature of the programmable skew is the

ability of outputs to lead or lag the REF input signal. The PI6C3Q991

has 8 programmable skew outputs in 4 banks of 2, while the

PI6C3Q993 has 6 programmable skew outputs and 2 zero skew

outputs. Skew is controlled by 3-level input signals that may be hard-

wired to appropriate HIGH-MID-LOW levels.

When the GND/sOE pin is held low, all the outputs are synchro-

nously enabled. However, if GND/sOE is held high, all the outputs

except 3Q0 and 3Q1 are synchronously disabled. Furthermore, when

the V

CCQ

/PE is held high, all the outputs are synchronized with the

positive edge of the REF clock input. When V

CCQ

/PE is held low,

all the outputs are synchronized with the negative edge of REF. Both

devices have LVTTL outputs with 12mA balanced drive outputs.

Pin Configurations

PI6C3Q991

REF

VCCQ

FS

PI6C3Q993

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

GND

TEST

2F1

2F0

GND/sOE

1F1

1F0

VCCN

1Q0

1Q1

GND

GND

2Q0

2Q1

3F1

4F0

4F1

VCCQ/PE

VCCN

4Q1

4Q0

GND

GND

4

5

6

7

8

9

10

11

12

13

14

1 32 31 30

29

28

27

26

32-Pin

25

J

24

23

22

21

15 16 17 18 19 20

3 2

2F0

GND/sOE

1F1

1F0

VCCN

1Q0

1Q1

GND

GND

3F0

3F1

VCCQ/PE

VCCN

4Q1

4Q0

GND

3Q1

3Q0

VCCN

FB

28-Pin

Q

23

22

21

20

19

18

17

16

15

1

PS8449A

10/09/00

next

P56C3Q991-5J相關(guān)型號(hào)PDF文件下載

• 型號(hào)
  版本
  描述
  廠(chǎng)商
  下載
• P56C3Q991-...
  英文版
  Eight Distributed-Output Clock Driver
  ETC
  P56C3Q991-5J

您可能感興趣的PDF文件資料

• P56C3Q991-5J

熱門(mén)IC型號(hào)推薦

• PQ070XZ1HZPH
• PXA270C5C520
• PMB6810V1.73
• PCF8582C-2T
• PDZ2.4B
• PCA9545APWR
• P87C51SBAA
• PMEG4010CEH
• PMN38EN
• P80C552EBA
• PHD21N06LT
• PBSS4140T