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P5504EVG Datasheet

  • P5504EVG

  • P-Channel Logic Level Enhancement Mode Field Effect Transist...

  • 298.08KB

  • 5頁

  • ETC

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NIKO-SEM
P-Channel Logic Level Enhancement
Mode Field Effect Transistor
P5504EVG
SOP-8
Lead-Free
D
PRODUCT SUMMARY
V
(BR)DSS
-40V
R
DS(ON)
55m惟
I
D
-5.5A
4
:GATE
5,6,7,8 :DRAIN
1,2,3 :SOURCE
G
S
ABSOLUTE MAXIMUM RATINGS (T
C
= 25
擄C
Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
1
Power Dissipation
T
C
= 25 擄C
T
C
= 70 擄C
Operating Junction & Storage Temperature Range
Lead Temperature (
1
/
16
鈥?from case for 10 sec.)
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
Junction-to-Ambient
1
2
SYMBOL
V
DS
V
GS
LIMITS
-40
鹵20
-5.5
-4.5
-20
2.5
1.3
-55 to 150
275
UNITS
V
V
T
C
= 25 擄C
T
C
= 70 擄C
I
D
I
DM
P
D
T
j
, T
stg
T
L
A
W
擄C
SYMBOL
R
胃JA
TYPICAL
MAXIMUM
50
UNITS
擄C / W
Pulse width limited by maximum junction temperature.
Duty cycle
鈮?/div>
1%
ELECTRICAL CHARACTERISTICS (T
C
= 25
擄C,
Unless Otherwise Noted)
PARAMETER
SYMBOL
TEST CONDITIONS
STATIC
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
1
Drain-Source On-State
Resistance
1
Forward Transconductance
1
V
(BR)DSS
V
GS(th)
I
GSS
I
DSS
I
D(ON)
R
DS(ON)
g
fs
V
GS
= 0V, I
D
= -250碌A(chǔ)
V
DS
= V
GS
, I
D
= -250碌A(chǔ)
V
DS
= 0V, V
GS
= 鹵20V
V
DS
= -32V, V
GS
= 0V
V
DS
= -30V, V
GS
= 0V, T
J
= 125 擄C
V
DS
= -5V, V
GS
= -10V
V
GS
= -4.5V, I
D
= -4.5A
V
GS
= -10V, I
D
= -5.5A
V
DS
= -10V, I
D
= -5.5A
-20
65
38
11
94
55
-40
-1
-1.5
-2.5
鹵250 nA
1
10
碌A(chǔ)
A
m惟
S
V
LIMITS
UNIT
MIN TYP MAX
SEP-30-2004
1

P5504EVG相關(guān)型號PDF文件下載

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  • 英文版
    P-Channel Logic Level Enhancement Mode Field Effect Transist...
    ETC
  • 英文版
    N-Channel Logic Level Enhancement Mode Field Effect Transist...
    ETC

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