音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

P520-10DC Datasheet

  • P520-10DC

  • Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xt...

  • 8頁(yè)

  • PLL

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

PLL520-10
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
65MHz to 130MHz Fundamental Mode Crystal.
Output range: 65MHz 鈥?800MHz (selectable 1x,
2x, 4x and 8x multipliers).
Low Injection Power for crystal 50uW.
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Integrated variable capacitors.
Supports 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
DIE CONFIGURATION
OUTSEL0^
65 mil
OUTSEL1^
SEL0^
SEL1^
VDD
VDD
VDD
VDD
(1550,1475)
17
16
25
24
23
22
21
20
19
18
GNDBUF
CMOS
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
OE_SEL^
XIN
XOUT
SEL3^
62 mil
26
27
Die ID:
A1313-13A
15
28
14
13
SEL2^
OE
CTRL
VCON
29
12
DESCRIPTION
PLL520-10 is a VCXO IC specifically designed to
pull frequency fundamental crystals from 65MHz to
130MHz, with an integrated Phase Locked Loop for
selectable 1x (no PLL), 2x, 4x or 8x multipliers. Its
design was optimized to tolerate higher limits of
interelectrode capacitance and bonding capacitance
to improve yield. It achieves very low current into the
crystal resulting in better overall stability. Its internal
varicaps allow an on chip frequency pulling,
controlled by the VCON input.
11
30
C502A
31
1
2
3
4
5
6
7
8
10
9
Y
(0,0)
X
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
SEL
OE
VCON
Oscillator
X+
X-
Amplifier
w/
integrated
varicaps
PLL
(Phase
Locked
Loop)
OUTPUT SELECTION AND ENABLE
OUTSEL1
(Pad #18)
0
0
1
1
OUTSEL0
(Pad
#25)
0
1
0
1
OE_CTRL
(Pad #30)
0
1 (Default)
0 (Default)
1
Tri-state
Output enabled
Output enabled
Tri-state
Selected Output
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
State
Q
Q
PLL by-pass
PLL520-10
OE_SELECT
(Pad #9)
0
1 (Default)
Pad #9: Bond to GND to set to 鈥?鈥? bond to VDD to set to 鈥?鈥?/div>
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad
#9) is 鈥?鈥?/div>
Logical states defined by CMOS levels if OE_SELECT is 鈥?鈥?/div>
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 1
GNDBUF
GND
GND
GND
GND
GND
NC
GND

P520-10DC相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    DIFFERENTIALTASTKOPF 100MHZ TEKTRONIX
    ETC
  • 英文版
    Digital Isolation Transformer
    ETAL
  • 英文版
    D-Sub Cable Assembly DB09 Beige, Individual (Round) 6.0' (1....
  • 英文版
    Low Phase Noise VCXO with multipliers (for 100-200MHz Fund X...
    PLL
  • 英文版
    Low Phase Noise VCXO with multipliers (for 100-200MHz Fund X...
    PLL
  • 英文版
    Low Phase Noise VCXO with multipliers (for 100-200MHz Fund X...
    PLL
  • 英文版
    Low Phase Noise VCXO with multipliers (for 100-200MHz Fund X...
    PLL
  • 英文版
    Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xt...
    PLL
  • 英文版
    Low Phase Noise VCXO (for 120-200MHz Fund Xtal)
    PLL
  • 英文版
    PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
    PLL
  • 英文版
    PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
    PLL
  • 英文版
    PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
    PLL
  • 英文版
    PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
    PLL

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！