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P502-26SC Datasheet

  • P502-26SC

  • High Pull-Range VCXO (27MHz) with integrated Audio PLL

  • 204.99KB

  • 5頁(yè)

  • PLL

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PLL502-26
High Pull-Range VCXO (27MHz) with integrated Audio PLL
FEATURES
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Low phase noise 27MHz VCXO (-135 dBc at
10kHz offset).
Integrated variable capacitors.
Wide pull range (+/- 250 ppm).
Low jitter (RMS): 10ps period.
Integrated audio Phase Locked Loop.
Audio clock output (ideal for 8.192MHz,
11.2896MHz, 12.288MHz).
27MHz crystal input.
Audio Reference clock input.
3.3V operation.
Available in 16-Pin SOIC.
PIN CONFIGURATION
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
N/C*
VDD_PLL
VDD_VCXO
XIN
XOUT
VCON
GND_VCXO
GND_PLL
1
2
N/C*
GND_27MHz
OUT_27MHz
VDD_27MHz
VDD_Audio
OUT_Audio
GND_Audio
REF_Audio
PLL502-26
3
4
5
6
7
8
DESCRIPTION
The PLL502-26 is a low cost, high pull-range and
low phase noise VCXO, providing less than -135dBc
at 10kHz offset at 27MHz. It also integrates an Audio
clock phase locked loop ideal for the 8.192MHz,
11.2896MHz and 12.288MHz audio outputs, starting
from an audio reference clock. Its very high pull
range makes it ideal for Digital Video applications,
allowing users to save board space and cost.
Note: *
Pins reserved for future DAC integration
OUTPUT RANGE
OUTPUT
VCXO
Audio
FREQUENCY RANGE
27MHz
8.192MHz 鈥?12.288MHz
OUTPUT
TYPE
CMOS
CMOS
BLOCK DIAGRAM
VCON
XIN
XOUT
VARICAP
XTAL
OSC
OUT_27MHz
REF_Audio
10X
PLL
OUT_Audio
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/17/04 Page 1

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    High Pull-Range VCXO (27MHz) with integrated Audio PLL
    PLL
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    Low Phase Noise VCXO (24MHz to 50MHz)
    PLL
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    Low Phase Noise VCXO (24MHz to 50MHz)
    PLL
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