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P500-27SC Datasheet

  • P500-27SC

  • Low Power CMOS Output VCXO Family (27MHz to 200MHz)

  • 5頁(yè)

  • PLL

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PLL500-27/-37/-47
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
FEATURES
鈥?/div>
VCXO output for the 27MHz to 200MHz range
-
PLL500-27: 27MHz to 65MHz
-
PLL500-37: 65MHz to 130MHz
-
PLL500-47: 100MHz to 200MHz
Low phase noise (-130 dBc @ 10kHz offset).
CMOS output with OE tri-state control.
Selectable output drive (Standard or High drive).
-
Standard: 12mA drive capability at TTL level.
-
High: 36mA drive capability at TTL level.
Fundamental crystal input.
Integrated high linearity variable capacitors.
+/- 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.5-3.3V operation.
Available in 8-Pin SOIC or DIE.
PIN CONFIGURATION
XIN
DRIVSEL^
VCON
GND
1
2
3
4
8
7
6
5
XOUT
OE^
VDD
CLK
PLL500-x7
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
^: Denotes internal Pull-up
DIE PAD LAYOUT
8
1
2
7
6
3
4
5
DESCRIPTION
The PLL500-27/-37/-47 are a low cost, high perform-
ance, low phase noise, and high linearity VCXO fam-
ily for the 27 to 200MHz range, providing less than -
130dBc at 10kHz offset. The very low jitter (2.5 ps
RMS period jitter) makes these chips ideal for appli-
cations requiring voltage controlled frequency
sources. The IC鈥檚 are designed to accept fundamen-
tal resonant mode crystals.
FREQUENCY RANGE
PART #
PLL500-27
PLL500-37
PLL500-47
MULTIPLIER
No PLL
No PLL
No PLL
FREQUENCY
27 鈥?65 MHz
65 鈥?130 MHz
100 鈥?200 MHz
BLOCK DIAGRAM
XIN
XOUT
XTAL
OSC
VARICAP
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/21/04 Page 1

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