鈥?/div>
^: Denotes internal Pull-up
DIE PAD LAYOUT
8
1
2
7
6
3
4
5
DESCRIPTION
The PLL500-27/-37/-47 are a low cost, high perform-
ance, low phase noise, and high linearity VCXO fam-
ily for the 27 to 200MHz range, providing less than -
130dBc at 10kHz offset. The very low jitter (2.5 ps
RMS period jitter) makes these chips ideal for appli-
cations requiring voltage controlled frequency
sources. The IC鈥檚 are designed to accept fundamen-
tal resonant mode crystals.
FREQUENCY RANGE
PART #
PLL500-27
PLL500-37
PLL500-47
MULTIPLIER
No PLL
No PLL
No PLL
FREQUENCY
27 鈥?65 MHz
65 鈥?130 MHz
100 鈥?200 MHz
BLOCK DIAGRAM
XIN
XOUT
XTAL
OSC
VARICAP
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/21/04 Page 1