P4C1256L
P4C1256L
LOW POWER 32K x 8
STATIC CMOS RAM
FEATURES
V
CC
Current (Commercial/Industrial)
鈥?Operating: 70mA/85mA
鈥?CMOS Standby: 100
碌
A/100
碌
A
Access Times
鈥?5/70 (Commercial or Industrial)
Single 5 Volts
鹵
10% Power Supply
Easy Memory Expansion Using
CE
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
鈥?8-Pin 600 mil DIP
鈥?8-Pin 330 mil SOP
DESCRIPTION
locations are specified on address pins A
0
to A
14
. Read-
ing is accomplished by device selection (CE and out-
put enabling (OE) while write enable (WE) remains
HIGH. By presenting the address under these condi-
tions, the data in the addressed memory location is pre-
sented on the data input/output pins. The input/output
pins stay in the HIGH Z state when either
CE
or
OE
is
Access times of 55 ns and 70 ns are available. CMOS HIGH or
WE
is LOW.
is utilized to reduce power consumption to a low level.
Package options for the P4C1256L include 28-pin 600
The P4C1256L device provides asynchronous opera- mil DIP and 28-pin 330 mil SOP packages.
tion with matching access and cycle times. Memory
The P4C1256L is a 262,144-bit low power CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V鹵10% tolerance power
supply.
FUNCTIONAL BLOCK DIAGRAM
ROW SELECT
A
鈥⑩€?鈥?/div>
PIN CONFIGURATION
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
(8)
A
262,144-BIT
MEMORY
ARRAY
A1
A2
A3
A4
A5
鈥⑩€⑩€?/div>
WE
A14
A13
A12
I/O1
鈥⑩€⑩€?/div>
鈥⑩€⑩€?鈥⑩€⑩€?/div>
A
11
OE
A
10
CE
I/0
8
I/0
7
I/0
6
I/0
5
I/0
4
INPUT
DATA
CONTROL
COLUMN I/O
A6
A7
A8
A9
鈥?鈥⑩€?/div>
鈥⑩€⑩€?/div>
I/O2
COLUMN
SELECT
I/0
1
I/0
2
I/0
3
GND
A
WE
鈥⑩€⑩€?/div>
鈥⑩€⑩€?/div>
CE
A
(7)
OE
DIP (P6), SOP (S11-2)
TOP VIEW
Means Quality, Service and Speed
1Q97
125
P4C1256L-70PI相關(guān)型號(hào)PDF文件下載
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