P4C1024L
P4C1024L
LOW POWER 128K x 8
CMOS STATIC RAM
FEATURES
V
CC
Current (Commercial/Industrial)
鈥?Operating: 70mA/85mA
鈥?CMOS Standby: 100
碌
A/100
碌
A
Access Times
鈥?5/70 (Commercial or Industrial)
Single 5 Volts
鹵
10% Power Supply
Easy Memory Expansion Using CE
1,
CE
2
and
OE Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
鈥?2-Pin 600 mil DIP
鈥?2-Pin 445 mil SOP
DESCRIPTION
The P4C1024L is a 1,048,576-bit low power CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V鹵10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS
is utilized to reduce power consumption to a low level.
The P4C1024L device provides asynchronous opera-
tion with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
16
. Read-
ing is accomplished by device selection (CE
1
low and
CE
2
high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory
location is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
The P4C1024L is packaged in a 32-pin 445 mil SOP
as well as a 600 mil PDIP.
FUNCTIONAL BLOCK DIAGRAM
ROW SELECT
A
鈥⑩€?鈥?/div>
PIN CONFIGURATION
NC
A16
A14
A12
A7
(9)
A
262,144-
BIT
MEMORY
ARRAY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE
1
I/O7
I/O6
I/O5
I/O4
I/O3
I/O
1
鈥⑩€⑩€?鈥⑩€⑩€?/div>
A6
INPUT
DATA
CONTROL
COLUMN
I/O
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
鈥⑩€⑩€?鈥⑩€⑩€?/div>
鈥?鈥⑩€?鈥?鈥?鈥?/div>
I/O
2
COLUMN
SELECT
WE
CE
1
CE2
OE
CONTROL
CIRCUIT
A
鈥⑩€⑩€?/div>
鈥⑩€⑩€?/div>
GND
A
(8)
DIP (P600), SOP (S12)
TOP VIEW
Means Quality, Service and Speed
1Q97
151
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