鈥?/div>
Four synchronous outputs
Selectable divider/multiplier
Output Enable control
Low phase error < 150 ps
Allows clock input to have spread spectrum modulation for
EMI reduction
Low output skew < 200 ps
Low cycle jitter < 200 ps
Industrial temperature (聳40擄C to 85擄C)
3.3V V supply
Packages: 24-pin QSOP (Q) and 24-pin TSSOP (L)
Product Description
PI6C2410 is a low skew, low jitter, PLL clock buffer with divider or
multiplier designed for PCI-X application in servers and worksta-
tions. There are two selectable input ranges using HF# input: 10-40
MHz and 40-80 MHz. All outputs are synchronized to the input and
to the other outputs. Each output can be independently turned off
to reduce EMI and power consumption.
Block Diagram
Pin Configuration
AGND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
CLKIN
AV
CC
V
CC
OUT0
OUT1
GND
GND
OUT2
OUT3
V
CC
OE3
OE2
OUT0
OUT1
V
CC
HF#
DIV0
DIV1
OUT2
OE[0:3]
HF#
CLKIN
FBIN
DIV[0:1]
PLL
DIV
FBOUT
OUT3
GND
GND
FBIN
FBOUT
V
CC
OE0
OE1
24-Pin
Q, L
19
18
17
16
15
14
13
20
Clock Select Table
HF#
1
1
1
1
0
0
0
0
D IV1
1
1
0
0
1
1
0
0
D IV0
1
0
1
0
1
0
1
0
OUTx
CLK IN
2xCLK IN
3xCLK IN
4xCLK IN
CLK IN/2
CLK IN
1.5xCLK IN
2xCLK IN
66MHz
33MHz
CLKIN
OUTx
33MHz
66MHz
100MHz
133MHz
33MHz
66MHz
100MHz
133MHz
1
PS8593
01/22/02