OR3LP26B Datasheet

IC型號：
OR3LP26B
PDF描述：
Field-Programmable System Chip (FPSC) Embedded Master/Target...
文件大小：
4231.82KB
PDF頁數(shù)：
184頁
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AGERE

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Data Sheet

March 2000

ORCA

廬

OR3LP26B Field-Programmable System Chip (FPSC)

Embedded Master/Target PCI Interface

Introduction

Lucent Technologies Microelectronics Group has

developed a solution for designers who need the

many advantages of an FPGA-based design imple-

mentation, coupled with the high bandwidth of an

industry-standard PCI interface. The

ORCA

OR3LP26B (a member of the Series 3+ FPSC family)

provides a full-featured 33/50/66 MHz, 32-/64-bit PCI

interface, fully designed and tested, in hardware, plus

FPGA logic for user-programmable functions.

Four internal FIFOs individually buffer both direc-

tions of both the Master and Target interfaces:

鈥?Both Master FIFOs are 64 bits wide by 32 bits

deep.

鈥?Both Target FIFOs are 64 bits wide by 16 bits

deep.

Capable of no-wait-state, full-burst PCI transfers in

either direction, on either the Master or Target

interface. The dual 64-bit data paths extend into

the FPGA logic, permitting full-bandwidth, simulta-

neous bidirectional data transfers of up to

528 Mbytes/s to be sustained indefinitely.

Can be configured to provide either two 64-bit

buses (one in each direction) to be multiplexed

between Master and Target, or four independent

32-bit buses.

Provides many hardware options in the PCI core

that are set during FPGA logic configuration.

Operates within the requirements of the PCI 5 V

and 3.3 V signaling environments and 3.3 V com-

mercial environmental conditions, allowing the

same device to be used in 5 V or 3.3 V PCI sys-

tems.

FPGA is reconfigurable via the PCI interface's con-

figuration space (as well as conventionally), allow-

ing the FPGA to be field-updated to meet late-

breaking requirements of emerging protocols.

PCI Bus Core Highlights

Implemented in an

ORCA

Series 3 OR3L125B

base array, displacing the bottom ten rows of 28

columns.

Core is a well-tested ASIC model.

Fully compliant to Revision 2.2 of PCI Local Bus

specification.

Operates at PCI bus speeds up to 66 MHz on a

32-/64-bit wide bus.

Comprises two independent controllers for Master

and Target.

Meets/exceeds all requirements for

PICMG

Hot

Swap friendly silicon, full Hot Swap model, per the

CompactPCI

Hot Swap specification,

PICMG

2.1

R1.0.

PCI SIG Hot Plug (R1.0) compliant.

PICMG

and

CompactPCI

are registered trademarks of the PCI

Industrial Computer Manufacturers Group.

Table 1.

ORCA

OR3LP26B PCI FPSC Solution鈥擜vailable FPGA Logic

Device

OR3LP26B

Usable Gates

鈥?/div>

60K鈥?20K

Number of Number of Max User Max User

LUTs

Registers

RAM

I/Os

4032

5304

64K

259

Array

Size

18 x 28

Number of

PFUs

504

鈥?The embedded core and interface comprise approximately 85K standard-cell ASIC gates in addition to these usable gates. The usable

gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only

gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12

gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic,

CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4

RAM (or 512 gates) per PFU.

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Field-Programmable System Chip (FPSC) Embedded Master/Target...

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OR3LP26B Datasheet

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