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OPB16450UART Datasheet

  • OPB16450UART

  • DS433 August 18, 2004 Product Specification

  • 15頁(yè)

  • XILINX   XILINX

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OPB 16450 UART
DS433 August 18, 2004
0
0
Product Specification
LogiCORE鈩?Facts
Core Specifics
Introduction
This document provides the specification for the OPB Uni-
versal Asynchronous Receiver/Transmitter (UART) Intellec-
tual Property (IP).
The UART described in this document has been designed
incorporating the features described in
National Semicon-
ductor PC16550D UART with FIFOs
data sheet (June,
1995), (http://www.national.com/pf/PC/PC16550D.html).
The National Semiconductor PC16550D data sheet is refer-
enced throughout this document and should be used as the
authoritative specification. Differences between the
National Semiconductor implementation and the OPB
UART Point Design implementation are highlighted and
explained in
Specification Exceptions
Supported Device
Family
Virtex-II Pro
鈩?/div>
, Virtex
鈩?/div>
,
Virtex-II
鈩?/div>
, Virtex-4
鈩?/div>
, QPro
鈩?/div>
-R
Virtex-II, QPro Virtex-II, Virtex-E,
Spartan-II
鈩?/div>
, Spartan-IIE
鈩?/div>
,
Spartan-3
鈩?/div>
opb_uart16450
Resources Used
Version of Core
v1.00c
Min
Slices
LUTs
341
357
347
0
Provided with Core
Max
341
357
347
0
Features
鈥?/div>
鈥?/div>
Hardware and software register compatible with all
standard 16450 UARTs
Implements all standard serial interface protocols
-
-
-
-
-
-
-
-
-
鈥?/div>
-
-
-
-
-
-
鈥?/div>
5, 6, 7, or 8 bits per character
Odd, Even, or no parity detection and generation
1, 1.5, or 2 stop bit detection and generation
Internal baud rate generator and separate receiver
clock input
Modem control functions
False start bit detection and recovery
Prioritized transmit, receive, line status, and
modem control interrupts
Line break detection and generation
Internal loop back diagnostic functionality
Receiver Buffer Register (Read Only)
Transmitter Holding Register (Write Only)
Interrupt Enable Register
Interrupt Identification Register (Read Only)
Line Control and Line Status Registers
Modem Control and Modem Status Registers
FFs
Block RAMs
Documentation
Design File Formats
Constraints File
Verification
Instantiation
Template
Reference Designs
Product Specification.
VHDL
N/A
N/A
N/A
None
Design Tool Requirements
Registers
Xilinx Implementation
Tools
Verification
Simulation
Synthesis
Support
5.1i or later
N/A
ModelSim SE/EE 5.6e or later
XST
Scratch Register
Support provided by Xilinx, Inc.
-
Divisor Latch (least and more significant byte)
漏 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS433 August 18, 2004
Product Specification
www.xilinx.com
1-800-255-7778
1

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