鈥?/div>
Bill of Materials
Board Lay鈭抲p
The SOT23, SC70, and SOIC8 evaluation boards are
implemented in two layers (Figure 1, Evaluation Board
Lay鈭抲p). The first layer is the 1.0 oz copper ground plane,
where a portion of the ground plane is cut out to mount the
device. The FR4 dielectric material is placed between the
first and second layer. The second layer contains the rest of
the components and primary signal traces.
Top Silkscreen
Top Soldermask
Top Plating
0.062 + / 鈭?0.010
01
Cu = 1 Oz, 0.0014
Adjust
02
Tw = 0.045, Zo = 50
W,
Cu = 1 Oz, 0.0014
Bottom Plating
Bottom Soldermask
Bottom Silkscreen
Bottom Metal
Top Metal
Figure 1. Evaluation Board Lay鈭抲p
Board Design
The evaluation board was designed for non鈭抜nverting op
amp configuration (Figure 2). The input contains
termination resistor R3 (usually 50
惟).
The input can also be
monitored through J1 when R1 and R2 are populated. The
evaluation board has versatile loading options for the op
amp through C9, R10, and R11 depending on the user鈥檚
preference it can be configured as capacitive load, series
resistance load, parallel resistance load, etc.
漏
Semiconductor Components Industries, LLC, 2005
1
July, 2005 鈭?Rev. 0
Publication Order Number:
OPAMP1EVB/D