Thermal Resistance 鈥?/div>
Junction鈥搕o鈥揂mbient (Note 3.)
Total Power Dissipation @ T
A
= 25擄C
Continuous Drain Current @ T
A
= 25擄C
Continuous Drain Current @ T
A
= 70擄C
Pulsed Drain Current (Note 4.)
Symbol
V
DSS
V
DGR
V
GS
R
胃JA
P
D
I
D
I
D
I
DM
R
胃JA
P
D
I
D
I
D
I
DM
R
胃JA
P
D
I
D
I
D
I
DM
Value
20
20
"12
62.5
2.0
6.5
5.5
20
102
1.22
5.07
4.07
16
172
0.73
3.92
3.14
12
Unit
V
V
V
8
G
S
1
擄C/W
W
A
A
A
擄C/W
W
A
A
A
擄C/W
W
A
A
A
SO鈥?
CASE 751
STYLE 11
MARKING DIAGRAM
& PIN ASSIGNMENT
Source 1
Gate 1
Source 2
Gate 2
1
2
3
4
(Top View)
E6N02
L
Y
WW
= Device Code
= Assembly Location
= Year
= Work Week
E6N02
LYWW
8
7
6
5
Drain 1
Drain 1
Drain 2
Drain 2
1. Mounted onto a 2鈥?square FR鈥? Board (1鈥?sq. 2 oz. Cu 0.06鈥?thick single
sided), t < 10 seconds.
2. Mounted onto a 2鈥?square FR鈥? Board (1鈥?sq. 2 oz. Cu 0.06鈥?thick single
sided), t = steady state.
3. Minimum FR鈥? or G鈥?0 PCB, t = steady state.
4. Pulse Test: Pulse Width = 300
ms,
Duty Cycle = 2%.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
ORDERING INFORMATION
Device
NTMD6N02R2
Package
SO鈥?
Shipping
2500/Tape & Reel
漏
Semiconductor Components Industries, LLC, 2000
1
November, 2000 鈥?Rev. 0
Publication Order Number:
NTMD6N02R2/D