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NTMD2P01R2 Datasheet

  • NTMD2P01R2

  • TRANSISTOR | MOSFET | MATCHED PAIR | P-CHANNEL | 16V V(BR)DS...

  • 8頁

  • ETC

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NTMD2P01R2
Product Preview
Power MOSFET
-2.3 Amps, -16 Volts
Dual SO鈥? Package
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
High Efficiency Components in a Single SO鈥? Package
High Density Power MOSFET with Low R
DS(on)
Logic Level Gate Drive
SO鈥? Surface Mount Package,
Mounting Information for SO鈥? Package Provided
http://onsemi.com
鈥?.3 AMPERES
鈥?6 VOLTS
100 mW @ V
GS
= 鈥?.5 V
P鈥揅hannel
D
Applications
鈥?/div>
Power Management in Portable and Battery鈥揚owered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones
MOSFET MAXIMUM RATINGS
(T
J
= 25擄C unless otherwise noted)
Rating
Drain鈥搕o鈥揝ource Voltage
Gate鈥搕o鈥揝ource Voltage 鈥?Continuous
Thermal Resistance 鈥?Junction鈥搕o鈥揂mbient
(Note 1)
Total Power Dissipation @ T
A
= 25擄C
Continuous Drain Current @ T
A
= 25擄C
Continuous Drain Current @ T
A
= 100擄C
Pulsed Drain Current (Note 4)
Thermal Resistance 鈥?Junction鈥搕o鈥揂mbient
(Note 2)
Total Power Dissipation @ T
A
= 25擄C
Continuous Drain Current @ T
A
= 25擄C
Continuous Drain Current @ T
A
= 100擄C
Pulsed Drain Current (Note 4)
Thermal Resistance 鈥?Junction鈥搕o鈥揂mbient
(Note 3)
Total Power Dissipation @ T
A
= 25擄C
Continuous Drain Current @ T
A
= 25擄C
Continuous Drain Current @ T
A
= 100擄C
Pulsed Drain Current (Note 4)
Operating and Storage
Temperature Range
Single Pulse Drain鈥搕o鈥揝ource Avalanche
Energy 鈥?Starting T
J
= 25擄C
(V
DD
= 鈥?6 Vdc, V
GS
= 鈥?.5 Vdc, Peak I
L
= 鈥?.0 Apk, L = 28 mH, R
G
= 25
鈩?
Maximum Lead Temperature for Soldering
Purposes, 1/8鈥?from case for 10 seconds
Symbol
V
DSS
V
GS
R
胃JA
P
D
I
D
I
D
I
DM
R
胃JA
P
D
I
D
I
D
I
DM
R
胃JA
P
D
I
D
I
D
I
DM
T
J
, T
stg
E
AS
Value
鈥?6
"10
175
0.71
鈥?.3
鈥?.45
鈥?.0
105
1.19
鈥?.97
鈥?.88
鈥?2
62.5
2.0
鈥?.85
鈥?.43
鈥?5
鈥?5 to
+150
350
Unit
V
V
擄C/W
W
A
A
A
擄C/W
W
A
A
A
擄C/W
W
A
A
A
擄C
mJ
G
S
MARKING
DIAGRAM
SO鈥?
CASE 751
STYLE 11
1
ED2P01
A
Y
WW
= Device Code
= Assembly Location
= Year
= Work Week
8
ED2P01
AYWW
PIN ASSIGNMENT
Source鈥?
Gate鈥?
Source鈥?
1
2
3
4
8
7
6
5
Drain鈥?
Drain鈥?
Drain鈥?
Drain鈥?
T
L
260
擄C
Gate鈥?
1. Minimum FR鈥? or G鈥?0 PCB, Steady State.
2. Mounted onto a 2鈥?square FR鈥? Board (1鈥?sq. 2 oz Cu 0.06鈥?thick single
sided), Steady State.
3. Mounted onto a 2鈥?square FR鈥? Board (1鈥?sq. 2 oz Cu 0.06鈥?thick single
sided), t
鈮?/div>
10 seconds.
4. Pulse Test: Pulse Width = 300
ms,
Duty Cycle = 2%.
Top View
ORDERING INFORMATION
Device
NTMD2P01R2
Package
SO鈥?
Shipping
2500/Tape & Reel
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
漏
Semiconductor Components Industries, LLC, 2001
1
October, 2001 鈥?Rev. 0
Publication Order Number:
NTMD2P01R2/D

NTMD2P01R2 產(chǎn)品屬性

  • 2,500

  • 分離式半導(dǎo)體產(chǎn)品

  • FET - 陣列

  • -

  • 2 個 P 溝道（雙）

  • 邏輯電平門

  • 16V

  • 2.3A

  • 100 毫歐 @ 2.4A，4.5V

  • 1.5V @ 250µA

  • 18nC @ 4.5V

  • 750pF @ 16V

  • 710mW

  • 表面貼裝

  • 8-SOIC（0.154"，3.90mm 寬）

  • 8-SOICN

  • 帶卷 (TR)

  • NTMD2P01R2OS

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