The NTE980 CMOS Micropower Phase鈥揕ocked Loop (PLL) consists of a low鈥損ower, linear voltage鈥?/div>
controlled oscillator (VCO) and two different phase comparators having a common signal鈥搃nput am-
plifier and a common comparator input in a 16鈥揕ead type package. A 5.2V zener diode is provided
for supply regulation if necessary.
= 10V, RI = 5k鈩?/div>
D
Low Frequency Drift: 0.04%/擄C (Typ) @ V
DD
= 10V
D
Choice of Two Phase Comparators:
Exclusive鈥揙R Network (I)
Edge鈥揅ontrolled Memory Network
w
/Phase鈥揚(yáng)ulse Output for Lock Indication (II)
D
High VCO Linearity: < 1% (Typ) @ V
DD
= 10V
D
VCO Inhibit Control for ON鈥揙FF Keying and Ultra鈥揕ow Standby Power Consumption
D
Source鈥揊ollower Output of VCO Control Input (Demod. Output)
D
Zener Diode to Assist Supply Regulation
D
Standardized, Symmetrical Output Characteristics
D
100% Tested for Quiescent Current at 20V
D
5V, 10V, and 15V Parametric Ratings
Applications:
D
FM Demodulator and Modulator
D
Frequency Synthesis and Multiplication
D
Frequency Discriminator
D
Signal Conditioning
D
D
D
D
FSK 鈥?Modems
Data Synchronization
Voltage鈥搕o鈥揊requency Conversion
Tone Decoding
Absolute Maximum Ratings:
DC Supply Voltage Range (Voltages referenced to V
SS
terminal), V
DD
. . . . . . . . . . . . 鈥?.5 to +20V
Input Voltage Range, All Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈥?.5 to V
DD
+0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
鹵10mA
Power Dissipation (T
A
= 鈥?0擄 to +60擄C), P
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW
T
A
= +60擄 to +85擄C . . . . . . . . . . . . . . . . . . . . . . . . . . . . Derate Linearly at 12mW/擄C to 200mW
Device Dissipation Per Output Transistor (T
A
= 鈥?0擄 to +85擄C) . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈥?0擄 to +85擄C
Storage Temperature Range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈥?5擄 to +150擄C
Lead Temperature (During Soldering, 1/16鈥?/div>
鹵1/32鈥?/div>
from case, 10sec Max), T
L
. . . . . . . . . . . +265擄C
1
2
3
4
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