NTE9672
Integrated Circuit
High Threshold Logic (HTL)
Quad, 2鈥揑nput NAND Gate
Description:
This NTE9672 is a Quad, 2鈥揑nput NAND gate with active output pull鈥搖p in a 14鈥揕ead DIP style pack-
age. The active output arrangement allows the circuit to handle capacitive loads at a higher speed
than is obtainable with a passive pullup configuration. Additionally, the impedance in the high state
is considerably less, and consequently makes this device more immune to electrical noise. The active
output configuration also allows for a more powerful arrangement to interface with discrete compo-
nents.
Electrical Characteristics:
(T
A
= +25擄C unless otherwise specified)
Parameter
Output Voltage
Symbol
V
OL
V
OH
Short鈥揅ircuit Current
Reverse Current
Output Leakage Current
Forward Current
Power Drain Current
Total Device
Switching Times
I
SC
I
R
I
CEX
I
F
I
CCL
I
CCH
t
1鈥?+
t
1+3鈥?/div>
I
OL
=12mA (Pulse In),
I
OH
= 鈥?.03mA (Pulse Out), V
CC
= 15V
Test Conditions
I
OL
= 12mA, V
IH
= 8.5V, V
CCL
= 14V
I
OH
= 鈥?.03mA, V
IL
= 6.5V, V
CC
= 15V,
V
CCL
= 14V
V
CCH
= 16V
V
R
= 16V, V
CCL
= 14V
V
CEX
= 16V
V
F
= 1.5V, V
R
= 16V, V
CCH
= 16V
V
CCH
= 16V
Min
鈥?/div>
12.5
鈥?.5
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Typ Max Unit
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1.5
鈥?/div>
鈥?5
2
100
鈥?.2
6
20
200
100
V
V
mA
碌A(chǔ)
碌A(chǔ)
mA
mA
mA
ns
ns
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