NTE861
Integrated Circuit
Quad, Normally Open, SPST JFET
Analog Switch
w
/Disable
Description:
The NTE861 is a monolithic combination of bipolar and JFET technology producing a one chip quad
JFET switch. A unique circuit technique is employed to maintain a constant resistance over the ana-
log voltage range of
鹵10V.
The input is designed to operate from minimum TTL levels, and switch
operation also ensures a break鈥揵efore鈥搈ake action.
Features:
D
Analog signals are not loaded
D
Constant 鈥淥N鈥?resistance for signals up to
鹵10V
and 100kHz
D
Pin compatible with CMOS switches with the advantage of blow out free handling
D
Small signal analog signals to 50MHz
D
Break鈥揵efore鈥搈ake action
D
High open switch isolation at 1.0MHz
D
Low leakage in 鈥淥FF鈥?state
D
TTL, DTL, RTL compatibility
D
Single disable pin opens all switches in package
This device operates from a
鹵15V
supply and swings a
鹵10V
analog signal. The JFET switches are
designed for applications where a dc to medium frequency analog signal needs to be controlled.
Absolute Maximum Ratings:
Positive Supply鈥揘egative Supply (V
CC
鈥揤
EE
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
EE
鈮?/div>
V
R
鈮?/div>
V
CC
Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
R
鈥?.0V
鈮?/div>
V
IN
鈮?/div>
V
R
+6.0V
Analog Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
EE
鈮?/div>
V
A
鈮?/div>
V
CC
+6V; V
A
鈮?/div>
V
EE
+36V
Analog Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
A
<
20mA
Power Dissipation (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0擄 to 70擄C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈥?5擄 to 150擄C
Typical Thermal Resistance, Junction鈥搕o鈥揂mbient, R
thJA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85擄C/W
Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300擄C
Note 1 For operating at high temperature this device must be derated based on a +100擄C maximum
junction temperature and a thermal resistance of +150擄C/W.
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