The NTE3880 is a third generation single chip microprocessor with unrivaled computational power.
This increased computational power results in higher system through鈥損ut and more efficient memory
utilization when compared to second generation microprocessors. In addition it is very easy to imple-
ment into a system because of it鈥檚 single voltage requirement plus all output signals are fully decoded
and timed to control standard memory or peripheral circuits. The circuit is implemented using an N鈥?/div>
channel, ion implanted, silicon gate MOS process.
This device has an internal register configuration which contains 208 bits of Read/Write memory that
are accessible to the programmer. The registers include two sets of six general purpose registers that
may be used individually as 8鈥揵it registers or as 16鈥揵it register pairs. There are also two sets of accu-
mulator and flag registers. The programmer has access to either set of main or alternate registers
through a group of exchange instructions. This alternate set allows foreground/background mode of
operation or may be reserved for very fast interrupt response. The NTE3880 also contains a 16鈥揵it
stack pointer which permits simple implementation of multiple level interrupts, unlimited subroutine
nesting and simplification of many types of data handling.
The two 16鈥揵it index registers allow tabular data manipulation and easy implementation of relocat-
able code. The Refresh register provides for automatic, totally transparent refresh of external dynam-
ic memories. The I register is used in a powerful interrupt response mode to form the upper 8 bits of
a pointer to a interrupt service address table, while the interrupting device supplies the lower 8 bits
of the pointer. An indirect call is then made to this service address.
Features:
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Single Chip, N鈥揅hannel Silicon Gate
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158 Instructions 鈥?Includes all 78 of the 8080A Instructions with Total Software Compatibility. New
Instructions Include 4鈥? 8鈥?and 16鈥揃it Operations with more useful Addressing Modes such as
Indexed, Bit and Relative
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17 Internal Registers
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Three Modes of Fast Interrupt Response plus a Non鈥揗askable Interrupt
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Directly Interfaces Standard Speed Static or Dynamic Memories with Virtually No External Logic
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1.0碌s Instruction Execution Speed
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Single 5VDC Supply and Single鈥揚(yáng)hase 5V Clock
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Out鈥揚(yáng)erforms any other Single鈥揚(yáng)hase 5V Clock
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All Pins TTL Compatible
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Built鈥揑n Dynamic RAM Refresh Circuitry
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