NTE2102
Integrated Circuit
NMOS, 1K Static RAM (SRAM), 350ns
Description:
The NTE2101 is a high鈥搒peed 1024 x 1 bit static random access read/write memory in a 16鈥揕ead
DIP type package designed using N鈥揅hannel depletion mode silicon gate technology. Static storage
cells eliminate the need for clock or refresh circuitry.
Low threshold silicon gate N鈥揅hannel technology allows complete DTL/TTL compatibility of all inputs
and outputs as well as a single 5V supply. The separate chip enable input (CE) controlling the output
allows easy memory expansion by OR鈥搕ying individual devices to a data bus. Data in and data out
have the same polarity.
Features:
D
Single 5V Supply
D
All Inputs and Outputs Directly DTL/TTL Compatible
D
Static Operation 鈥?No Clocks or Refresh
D
All Inputs Protected Against Static Charge
D
350ns Access Time
Absolute Maximum Ratings:
(Note 1)
Voltage at Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V to +7V
Power Dissipation, P
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Storage Temperature Range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 鈥?5擄 to +150擄C
Lead Temperature (During Soldering, 10sec), T
L
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300擄C
Note 1. 鈥淎bsolute Maximum Ratings鈥?are those values beyond which the device may be permanently
damaged. They do not mean the device may be operated at these values.
Recommended Operating Conditions:
Parameter
Supply Voltage
Operating Ambient Temperature
Input Low Voltage
Input High Voltage
Symbol
V
CC
T
A
V
IL
V
IH
Test Conditions
Min
4.75
0
鈥?.5
2.0
Typ
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Max
5.25
+70
0.8
V
CC
Unit
V
擄C
V
V
1
2
3
