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NTD85N02R Datasheet

  • NTD85N02R

  • Power MOSFET 85 Amps, 24 Volts N-Channel DPAK

  • 10頁

  • ONSEMI

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NTD85N02R
Power MOSFET
85 Amps, 24 Volts
N鈭扖hannel DPAK
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
http://onsemi.com
V
DSS
24 V
R
DS(ON)
TYP
4.8 mW
I
D
MAX
85 A
Pb鈭扚ree Packages are Available
Planar HD3e Process for Fast Switching Performance
Low R
DS(on)
to Minimize Conduction Loss
Low C
iss
to Minimize Driver Loss
Low Gate Charge
N鈭扖hannel
D
MAXIMUM RATINGS
(T
J
= 25擄C Unless otherwise specified)
Parameter
Drain鈭抰o鈭扴ource Voltage
Gate鈭抰o鈭扴ource Voltage 鈭?Continuous
Thermal Resistance 鈭?Junction鈭抰o鈭扖ase
Total Power Dissipation @ T
C
= 25擄C
Drain Current
Continuous @ T
C
= 25擄C, Limited by Package
Continuous @ T
A
= 25擄C, Limited by Wires
Single Pulse (t
p
鈮?/div>
10
ms)
Thermal Resistance, Junction鈭抰o鈭扐mbient
(Note 1)
Total Power Dissipation @ T
A
= 25擄C
Drain Current 鈭?Continuous @ T
A
= 25擄C
Thermal Resistance, Junction鈭抰o鈭扐mbient
(Note 2)
Total Power Dissipation @ T
A
= 25擄C
Drain Current 鈭?Continuous @ T
A
= 25擄C
Operating and Storage Temperature Range
Single Pulse Drain鈭抰o鈭扴ource Avalanche
Energy 鈭?Starting T
J
= 25擄C
(V
DD
= 30 V
dc
, V
GS
= 10 V
dc
, I
L
= 13 A
pk
,
L = 1 mH, R
G
= 25
W)
Maximum Lead Temperature for Soldering
Purposes, 1/8鈥?from Case for 10 Seconds
Symbol
V
DSS
V
GS
R
qJC
P
D
I
D
I
D
I
DM
R
qJA
P
D
I
D
R
qJA
P
D
I
D
T
J
, T
stg
E
AS
Value
24
鹵20
1.6
78.1
85
32
96
52
2.4
16
100
1.25
12
鈭?5 to
150
85
Unit
V
dc
V
dc
擄C/W
W
A
A
A
擄C/W
1 2
W
A
擄C/W
W
A
擄C
mJ
1
T
L
260
擄C
3
2
1 Gate
2 Drain
3 Source
4 Drain
3
DPAK
CASE 369C
STYLE2
S
G
4
4
1
2
3
DPAK鈭?
CASE 369D
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENTS
4
YWW
85
N02
YWW
85
N02
1
2
3
4
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
1. When surface mounted to an FR4 board using 1 inch pad size,
(Cu Area 1.127 in
2
).
2. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in
2
).
Y
= Year
WW
= Work Week
85N02R = Specific Device Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2004
1
September, 2004 鈭?Rev. 6
Publication Order Number:
NTD85N02R/D

NTD85N02R 產(chǎn)品屬性

  • 75

  • 分離式半導(dǎo)體產(chǎn)品

  • FET - 單

  • -

  • MOSFET N 通道，金屬氧化物

  • 邏輯電平門

  • 24V

  • 12A

  • 5.2 毫歐 @ 20A，10V

  • 2V @ 250µA

  • 17.7nC @ 5V

  • 2050pF @ 20V

  • 1.25W

  • 表面貼裝

  • TO-252-3，DPak（2 引線+接片），SC-63

  • D-Pak

  • 管件

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