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NSBMC096VF Datasheet

  • NSBMC096VF

  • NSBMC096-16/-25/-33 Burst Memory Controller

  • 268.31KB

  • 18頁

  • NSC

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NSBMC096-16 -25 -33 Burst Memory Controller
August 1993
NSBMC096-16 -25 -33 Burst Memory Controller
General Description
The NSBMC096 Burst Memory Controller is an integrated
circuit which implements all aspects of DRAM control for
high performance systems using an i960
CA CF
SuperScalar Embedded Processor The NSBMC096 is func-
tionally equivalent to the V96BMC
TM
The extremely high instruction rate achieved by these proc-
essors place extraordinary demands on memory system de-
sign if maximum throughput is to be sustained and costs
minimized
Static RAM offers a simple solution for high speed memory
systems However high cost and low density make this an
expensive and space consumptive choice
Dynamic RAMs are an attractive alternative with higher den-
sity and low cost Their drawbacks are slower access time
and more complex control circuitry required to operate
them
The access time problem is solved if DRAMs are used in
page mode In this mode access times rival that of static
RAM The control circuit problem is resolved by the
NSBMC096
The function that the NSBMC096 performs is to optimally
translate the burst access protocol of the i960 CA CF to the
page mode access protocol supported by dynamic RAMs
The device manages one or two-way interleaved arrange-
ments of DRAMs such that during burst access data can be
read or written at the rate of one word per system clock
cycle
The NSBMC096 has been designed to allow maximum flexi-
bility in its application The full range of processor speeds is
supported for a wide range of DRAM speeds sizes and or-
ganizations
No glue logic is required because the bus interface is cus-
tomized to the i960 CA CF System integration is further
enhanced by providing a 24-bit heartbeat timer and a bus
watch timer on-chip
The NSBMC096 is packaged as a 132-pin PQFP with a foot-
print of only 1 3 square inches It reduces design complexi-
ty space requirements and is fully derated for loading tem-
perature and voltage
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Interfaces directly to the i960 CA
Integrated Page Cache Management
Manages Page Mode Dynamic Memory devices
On-chip Memory Address Multiplexer Drivers
Supports DRAMs trom 256 kB to 64 MB
Bit counter timer
Non-interleaved or two way interleaved operation
5-Bit Bus Watch Timer
Software-configured operational parameters
High-Speed Low Power CMOS technology
Block Diagram
TL V 11805 鈥?1
This document contains information concerning a product that has been developed by National Semiconductor Corporation V3 Corporation This information
is intended to help in evaluating this product National Semiconductor Corporation V3 Corporation reserves the right to change and improve the specifications
of this product without notice
TRI-STATE is a registered trademark of National Semiconductor Corporation
NSBMC096
TM
and WATCHDOG
TM
are trademarks of National Semiconductor Corporation
i960 is a registered trademark of Intel Corporation
V96BMC
TM
is a trademark of V3 Corporation
C
1995 National Semiconductor Corporation
TL V 11805
RRD-B30M115 Printed in U S A

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