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NS32FX200VF Datasheet

  • NS32FX200VF

  • System Controller

  • 94頁

  • NSC

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NS32FX100-15 NS32FX100-20 NS32FV100-20 NS32FV100-25
NS32FX200-20 NS32FX200-25 System Controller
PRELIMINARY
July 1992
NS32FX100-15 NS32FX100-20 NS32FV100-20
NS32FV100-25 NS32FX200-20 NS32FX200-25
System Controller
General Description
The NS32FX200 NS32FV100 and NS32FX100 are highly
integrated system chips designed for a FAX system based
on National Semiconductor鈥檚 embedded processors
NS32FX161 NS32FV16 or NS32FX164 The NS32FX100 is
the common core for all three system chips The
NS32FV100 and NS32FX200 offer additional functions
Throughout this document references to the NS32FX100
also apply to both the NS32FV100 and the NS32FX200
Specific NS32FV100 or NS32FX200 features are explicitly
indicated
The NS32FX200 NS32FV100 and NS32FX100 feature an
interface to devices like stepper motors printers and scan-
ners a Sigma-Delta CODEC an elapsed-time counter a
DMA controller an interrupt controller and a UART
The NS32FX200 is optimized for high-end FAX applications
such as plain-paper FAX and multifunctional peripherals
The NS32FX100 is optimized for low-cost FAX applica-
tions The NS32FV100 is optimized for thermal paper FAX
machines with Digital Answering Machine support
Y
Y
Y
Y
Y
Y
Y
Features
Y
Y
Y
Y
Y
Y
Direct interface to the NS32FX161 NS32FV16 and
NS32FX164 embedded processors
Supports a variety of Contact Image Sensor (CIS) and
Charge Coupled Device (CCD) scanners
Direct interface to a variety of Thermal Print Head
(TPH) printers Bitmap shifter and DMA channels facili-
tate the connection of other types of printers
Supports two stepper motors
Direct interface to ROM and SRAM The NS32FX200
and NS32FV100 in addition interface to DRAM
devices
Y
Y
Y
Y
Y
Programmable wait state generator
Demultiplexed address and data buses
Multiplexed DRAM address bus (NS32FX200 and
NS32FV100)
Supports 3V freeze mode by maintaining only elapsed
time counter
Control of power consumption by disabling inactive
modules and reducing the clock frequency
Operating frequency
Normal mode 19 6608 MHz 24 576 MHz in steps
of 1 2288 MHz (NS32FX200)
Normal mode 19 6608 MHz 24 576 MHz in steps
of 1 2288 MHz (NS32FV100)
Normal mode 14 7456 MHz 19 6608 MHz in steps
of 1 2288 MHz (NS32FX100)
Power Save mode Normal mode frequency divided
by sixteen
On-Chip full duplex Sigma-Delta CODEC with
Total harmonic distortion better than
b
70 dB
Programmable hybrid balance filter
Programmable reception and transmission filters
Programmable gain control
On-Chip Interrupt Control Unit with
16 interrupt sources
Programmable triggering mode
On-Chip counters WATCHDOG
TM
UART
MICROWIRE
TM
System Clock Generator and I O
ports
On-Chip DMA controller (NS32FX200 four channels
NS32FX100 NS32FV100 three channels)
Up to 37 on-chip general purpose I O pins expandable
externally
Flexible allocation of I O and modules鈥?pins
132-pin JEDEC PQFP package
TL EE 11331 鈥?1
FIGURE 1-1 A FAX Controller Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRE
TM
and WATCHDOG
TM
are trademarks of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL EE11331
RRD-B30M105 Printed in U S A

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